| 摘要(英) |
When a problem occurring on a wafer, it can be divided into two kinds of errors, random and systematic. In the study, we use previously proposed boomerang chart to classify the problem of real wafer (WM-811K).
With the advancement of technology, the processes are more advanced, wafer size and quantity are also increased. Therefore, in the construction of boomerang chart, it is necessary to simulate a larger number and more different sizes of randomness wafer maps. We must improve the algorithm and increase the speed of the operation to meet the trend of technology.
However, NCL, one of the two important parameters of boomerang chart—NBD (number of bad die) and NCL (number of contiguous line), planned by a bad strategy in previous algorithm in the process of formulating the algorithm according to the original definition. Thus, it would cause time-consuming badly. When the number of random types increase and the wafer size becomes larger, the operation time would increase nonlinearly. Therefore, the research is going to develop a new search flow without violating the original definition and designs a new algorithms to improve the problem of increasing time in simulate larger randomness wafer map.
The new search strategy not only provides clear and detailed search rules, but also improves the speed of calculations larger randomness wafer map. When developing algorithms, it achieves significant acceleration. Furthermore, the algorithm can be easily implemented in various programming languages as well.
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| 參考文獻 |
[1] J.E. Chen, M.J. Wang, Y.S. Chang, S.C. Shyu, and Y.Y. Chen, “Yield Improvement by Test Error Cancellation ”, Proceedings of the Fifth Asian Test Symposium (ATS’96), pp.258-262, Nov. 1996.
[2] C.K. Hsu, F. Lin, K.T. Cheng, W. Zhang, X. Li, J.M. Carulli, and K.M. Butler, “Test data analytics - Exploring spatial and test-item correlations in production test data”, in International Test Conference (ITC), pp.1-10, Sep. 2013.
[3] M.J. Wu, J.S.R. Jang, and J.L. Chen, “Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-scale Datasets”, in IEEE Transactions on Semiconductor Manufacturing, vol.28, no.1, pp.1-12, Feb. 2015.
[4] F. Lin, C.K. Hsu, and K.T. Cheng, “Learning from Production Test Data: Correlation Exploration and Feature Engineering”, in Asian Test Symposium (ATS), pp.236-241, Nov. 2014.
[5] F. Lin, C.K. Hsu, and K.T. Cheng, “Feature engineering with canonical analysis for effective statistical tests screening test escapes”, in International Test Conference (ITC), pp.1-10, Oct. 2014.
[6] 林正田, “Wafer Map Analysis from a Random-Defect-Source Perspective” ，碩士論文，中央大學，2012.
[7] 曾國銓, “A Non-uniformly Distributed Defect Map Analysis by Quantification Model” ，碩士論文，中華大學，2013.
[8] 蕭寶威, “Wafer Map Analysis from Random Distributed Defects” ，碩士論文，中央大學，2016.
[9] 葉昱緯, “Application of Boomerang Chart to Real-World Mass Production Wafer Maps” ，碩士論文，中央大學，2016.
[10] 林威沅, “Verification of B-score Randomness by Synthetic Random Wafer Maps and Application to Special Patterns” 碩士論文，中央大學，2019.
[11] 黃昱凱, “Acceleration Core for the Calculation of the Randomness Features of Wafer Maps ” 碩士論文，中央大學，2019.
[12] 胡濠鑛, “ Consistency Analysis of Randomness Test for Rotating and Flipping Wafer Maps” 碩士論文，中央大學，2019.
[13] 鄭育典, “An Accelerated C-Core for Calculating the Cluster Number in Wafer Map Analysis” 碩士論文，中央大學，2018.
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