| 摘要(英) |
In this thesis, we find the relationship between diesize and Boomerang Chart based on wafer map which random distribution of defects, build the model by the relationship that let user just provided diesize to get bound of wafer cause by random defects to achieve the aim of discrimination abnormal wafers fast.
At first, we use the largest diesize to simulate bound accurately and carefully. We chose two linear regressions for this diesize. And by adjusting the offset of the center line of the bar graph with the wafer size, the center point at different sizes is corrected to prevent the center point deviation in the randomness analysis, and the offset of the center line for each diesize has a special relationship. Additionally, the standard deviation value is re-adjusted to meet the desired confidence interval percentage. Model based on the two factors to let user get bound of Boomerang Chart fast for full yield range, wider diesize and accurately has been provided.
Then, we generate synthetic wafer by random number. Increasing the original standard deviation of 1.96 times (95% confidence interval) to 2.58 times (99% confidence interval) and 3.89 times (99.99% confidence interval). We use full-range analysis to enhance the verification of randomness. And then verify the normality of normalized NBD to observe whether distribution of B-score meets to our critical points. By these steps, verified B-score is a standard score.
At last, the results of the previous thesis are compared with our method and our error function is used to quantify the difference between these to show the extent of improvement in this thesis.
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| 參考文獻 |
[1] Jwu-E Chen, Mill-Jer Wang, Yen-Shung Chang, Shaw Cherng Shyu, and Yung-Yuan Chen, “ Yield Improvement by Test Error Cancellation ”, in Test Symposium (ATS), pp.258-260, Nov. 1996.
[2] C. - K. Hsu, Lin, F., Cheng, K. - T. Tim, Zhang, W., Li, X., Carulli, J. M., and Butler, K. M., “Test data analytics - Exploring spatial and test-item correlations in production test data”, in Test Conference (ITC), pp.1-10, Sep. 2013.
[3] Ming-Ju Wu, Jyh-Shing Roger Jang, and Jui-Long Chen, “Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-scale Datasets”, IEEE Transactions on Semiconductor Manufacturing, vol.28, no.1, pp.1-12, Feb. 2015.
[4] F. Lin, Hsu, C. - K., and Cheng, K. - T. Tim, “Learning from Production Test Data: Correlation Exploration and Feature Engineering”, in Test Symposium (ATS), pp.236-241, Nov. 2014.
[5] F. Lin, Hsu, C. - K., and Cheng, K. - T. Tim, “Feature engineering with canonical analysis for effective statistical tests screening test escapes”, in Test Conference (ITC), pp.1-10, Oct. 2014.
[6] Takeshi Nakazawa, and Deepak V. Kulkarni, “Wafer Map Defect Pattern Classification and Image Retrieval Using Convolutional Neural Network”, in IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 31, NO. 2, MAY 2018
[7] 林正田,“Wafer Map Analysis from a Random-Defect-Source Perspective”,碩士論文﹐中央大學﹐2012.
[8] 曾國銓,“A Non-uniformly Distributed Defect Map Analysis by Quantification Model” , 碩士論文﹐中華大學﹐2013
[9] 蕭寶威,“Wafer Map Analysis from Random Distributed Defects”, 碩士論文﹐中央大學﹐2016.
[10] 葉昱緯,“Application of Boomerang Chart to Real-World Mass Production Wafer Maps”, 碩士論文﹐中央大學﹐2016.
[11] 吳雅軒,“Wafer Map Partition Analysis to Enhance Systematic Error Resolution”, 碩士論文﹐中央大學﹐2018.
[12] 林敬儒,“Identification of the Classifier for the Pattern of Spatial Randomness”, 碩士論文﹐中央大學﹐2018.
[13] 林威沅 ,“Verification of B-score Randomness by Synthetic Random Wafer Maps and Application to Special Patterns”, 碩士論文﹐中央大學﹐2019.
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