具對稱波偵測器之10 Gbps全速率四階脈波振幅調變資料與時脈回復電路

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姓名

劉威廷(Wei-Ting Liu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具對稱波偵測器之10 Gbps全速率四階脈波振幅調變資料與時脈回復電路
(A 10 Gbps Full Rate PAM-4 Clock and Data Recovery with Symmetric Edge Detector)

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至系統瀏覽論文 (2024-7-31以後開放)

摘要(中)

隨著科技的日新月異，電腦發展以及半導體產業的日益發展，數位資料的傳輸速度也快速提高，因此傳統的並列傳輸受制於其需要耗費大面積的特性，所以已經不敷高速數位傳輸系統使用故目前多採串列方式傳輸。因為傳輸資料提升，電路設計的困難度也大大提升。目前高速串列傳輸有許多規格可以參考，例如PCI-Express、SATA、USB或是光纖網路中的SONET等規格都是目前常用的設計標準，在最新世代的規格中，資料傳輸的速度甚至達到百億位元每秒等級，並將電路設計的複雜度帶到另一個新高度。
本論文參考USB 3.1 Gen2實現一個針對四階脈波振幅調變的對稱波偵測技術之全速率資料與時脈回復電路，並提出四階脈波振幅調變之全新相位偵測器。過去文獻中利用大量電路偵測四階脈波振幅調變訊號，將導致整體功耗上升，本論文將四階脈波振幅調變之邊緣加以區分，把不具相關性的邊緣忽略，使得還原時脈抖動能有效降低。另外提出新的轉態偵測器，借用單一邏輯閘即可達到轉態偵測的效果，且將其與傳統二進位相位偵測器做結合，可使得整體電路面積減少及功耗下降。本論文的設計使用TSMC 40 nm (TN40G) 1P10M CMOS製程，操作電壓為0.9 V，輸入資料為10 Gbps PAM-4，還原時脈速率為5 GHz，還原時脈之峰對峰值27.5 pspp，方均根值4.31 psrms，功率消耗為24.7 mW，晶片面積為1.11 mm2，核心電路面積為0.094 mm2。

摘要(英)

In recent years, according to the rapid development of the process and computers, the series data transmission is widely used for the bus instead of the parallel transmission and the data rate increases progressively, such as PCI-Express, SATA, USB and SONET in the fiber network. The data rate has even risen up to ten billion bits per second in the latest generation specifications. Therefore, the circuit design complexity is greatly increased.
In this paper, a full-rate data and clock recovery circuit for symmetric edge detection technique of PAM-4 is implemented with reference to USB 3.1 Gen2, and a new phase detector for PAM-4 is proposed. A large number of circuits are used to detect the PAM-4 signal, which leads to increase in overall power consumption. In addition, the edge of the PAM-4 is differentiated, so that the undesired edges are ignored, so that the recovered clock jitter is reduced. Moreover, a new transition detector is proposed, which uses only a single logic gate to achieve the effect of the transition detection, and combines it with the traditional bang-bang phase detector to reduce the overall circuit area and reduce the power consumption. This paper uses TSMC 40 nm (TN40G) 1P10M CMOS process, the operating voltage is 0.9 V, the input data is 10 Gbps PAM-4, the recovered clock rate is 5 GHz, the peak value of the recovered clock is 27.5 pspp, and the root mean square value is 4.31 psrms. The power consumption is 24.7 mW, the chip area is 1.11 mm2, and the core area is 0.094 mm2.

關鍵字(中)

★ 資料與時脈回復電路
★ 四階脈波振幅調變
★ 全速率
★ 相位偵測器

關鍵字(英)

★ Clock and Data Recovery
★ PAM-4
★ Full-Rate
★ Phase Detector

論文目次

摘要 i
Abstract ii
目錄 iii
圖目錄 vii
表目錄 x
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 4
第2章高速串列傳輸之訊號完整性 5
2.1 基本觀念 5
2.1.1 隨機二元資料之型態[4] 5
2.1.2 隨機二元資料之特性 6
2.1.3 資料編排形式[4] 7
2.2 時脈抖動簡介[36] 8
2.2.1 隨機性抖動(Random Jitter, RJ) 9
2.2.2 定量性抖動(Deterministic Jitter, DJ) 10
2.2.3 抖動量測的方法[36] 13
2.3 眼圖分析[4] 18
2.4 誤碼率 19
第3章資料與時脈回復電路之背景簡介 21
3.1 資料與時脈回復電路相關概念簡介 21
3.1.1 資料型態 21
3.1.2 相位偵測器型態 22
3.1.3 取樣速率 23
3.1.4 抖動轉移函數(Jitter Transfer, JTF)[20] 24
3.1.5 抖動容忍度(Jitter Tolerance, JTOL)[20] 25
3.2 傳統資料與時脈回復電路 26
3.2.1 鎖相迴路式資料與時脈回復電路[18]-[19] 26
3.2.2 混合鎖相迴路/延遲鎖相迴路式資料與時脈回復電路[20]-[21] 28
3.2.3 超取樣式資料與時脈回復電路[22] 29
3.2.4 相位選擇式資料與時脈回復電路[23] 30
3.2.5 雙路徑式資料與時脈回復電路[24] 31
3.3 四階脈波振幅調變之文獻探討 32
3.3.1 利用最小均方誤差準則之資料與時脈回復電路[30] 32
3.3.2 利用積分及轉態偵測之四方之一速率資料與時脈回復電路[31] 33
3.3.3 比較與討論 34
第4章具對稱波偵測器之四階脈波振幅調變資料與時脈回復電路設計與實現 37
4.1.1 電路架構 37
4.2 操作說明 39
4.2.1 四階脈波與非歸零式資料對二進位相位偵測器之影響 39
4.2.2 四階脈波之邊緣探討 40
4.2.3 四階脈波振幅調變之轉態偵測器 41
4.3 系統分析 43
4.3.1 頻率資訊鎖相迴路系統分析 43
4.3.2 資料與時脈回復電路系統分析 46
4.4 行為模擬 53
4.5 子電路介紹 55
4.5.1 對稱波偵測技術之二進位相位偵測器 55
4.5.2 相位頻率偵測器 57
4.5.3 電荷幫浦 58
4.5.4 電壓控制振盪器 60
4.5.5 除頻器 62
4.5.6 擺幅轉換電路[36] 63
4.6 模擬結果 64
4.6.1 操作在10 Gbps之全速率資料與時脈回復電路模擬 65
4.6.2 抖動容忍度模擬 68
第5章晶片佈局 71
5.1 電路佈局 71
5.1.1 晶片封裝 72
5.1.2 佈局與電源規劃 74
5.2 量測考量 75
5.2.1 量測環境 75
5.2.2 印刷電路板 76
5.2.3 高頻輸出緩衝器 77
5.2.4 低頻輸出緩衝器 79
5.2.5 高頻輸入端 80
5.2.6 抖動容忍度考量 81
5.3 規格比較表 81
第6章結論 85
6.1 結論 85
6.2 未來研究方向 – 迴路延遲及自動化 86
參考文獻 87

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2019-8-19

推文