適用於多標準電子設備且具相位補償技術之全數位展頻時脈產生器

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：10

、訪客IP：18.191.200.145

姓名

項學華(Hsueh-Hua Hsiang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

適用於多標準電子設備且具相位補償技術之全數位展頻時脈產生器
(An All-Digital Spread-Spectrum Clock Generator with Phase Compensation Technique for Multi-Standard Devices)

相關論文

★ 一種應用於觸控液晶顯示器的新型嵌入式開關	★ 多重相位之延遲鎖定迴路倍頻器設計與分析
★ 2.5Gbps串列收發器設計	★ 具低抖動與可適應式頻寬之自我偏壓鎖相迴路設計
★ 應用於串列傳輸之2.5GB/s CMOS 超取樣資料回復電路	★ 全數位任意責任週期之同步映射延遲電路
★ 全數位式互補金屬氧化半導自我取樣延遲線電路用於時脈抖動量測	★ 500MHz,30個相位輸出之鎖相迴路應用於三倍超取樣時脈回復系統
★ 設計於90奈米製程輸出頻率為100MHz-1GHz之具可適應性頻寬鎖相迴路	★ 高解析度可變動責任週期之同步複製延遲電路
★ 奈米CMOS晶片內序列傳輸之接收器	★ 奈米CMOS晶片內序列傳輸之送器
★ 基於鎖相迴路之多重相位脈波產生器	★ 低能量時脈儲存元件之分析、設計與量測
★ 具有預先增強器之Gbps串列連結傳送器及全數位超取樣資料回復器	★ 應用於10Gbps晶片系統傳輸鏈之低抖動自我校準鎖相迴路設計

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

至系統瀏覽論文 (2024-7-31以後開放)

摘要(中)

近年來，消費性電子產品的快速崛起帶動了資料傳輸速率的提升，為了滿足更高速的資料傳輸頻寬，高速串列傳輸技術已然成為現今主要資料傳輸技術。但隨著電子裝置的操作頻率日漸提升，電磁干擾(Electromagnetic Interference, EMI)效應越來越嚴重。在時脈產生電路中，由於集中的能量所造成的電磁干擾也將成為傳輸系統介面中的主要雜訊來源，因此，為了降低電磁干擾效應，展頻時脈技術已廣泛的應用於時脈產生器中。
此外，目前有線收發技術應用須具備向下相容的能力，這驅使設計一個具寬範圍操作之時脈產生器用以支援數種世代規格。因此，本論文參考SATA Gen1至Gen3規格，實現一個使用分數型鎖相迴路，並可適用於多世代規格之全數位展頻時脈產生器。論文中，提出具雙重相位旋轉之相位補償技巧應用於分數除頻器，針對相位補償技術應用於多規格時因為展頻之頻率範圍不同導致電磁干擾抑制能力劣化之缺陷做改良。透過相位旋轉，可有效補償瞬時時序錯誤，同時避免量化誤差的產生，實現一無擾動的真實分數除率。本論文使用TSMC 40 nm (TN40G) 1P9M CMOS製程實現，操作電壓為 0.9 V，中心操作頻率分別為6 GHz、3 GHz及1.5 GHz，並以頻率32.89 kHz之三角波作為調變訊號，向下展頻5000 ppm。展頻機制開啟後，電磁干擾抑制量分別約為22.4 dB、20.5 dB、18.8 dB。電路操作在最高頻率時的功率消耗為9.74 mW，整體晶片面積為0.9 mm2，核心電路所佔面積為0.0395 mm2。

摘要(英)

Recently, the rapid development of consumer electronics has led to higher transmission data rates. The high-speed serial link (HSSL) technology has become the major technique in modern data transmission to satisfy with the wider bandwidth of the transmission data. Additionally, as the operating frequency increases, the electromagnetic interference (EMI) induced by the concentrated energy of the clock generator will interfere the other equipment severely. It will be the main noise source in the transmission system. Thus, to reduce the EMI, the spread-spectrum clock generator (SSCG) has been widely employed for clock generation.
In the current wireline SerDes application, it evolves the coexistence of several specification generations. As a result, a wide range clock generator to support multi-specification generations is desirable. Therefore, this thesis presents an all-digital spread-spectrum clock generator (ADSSCG) based on a fractional-N all-digital PLL (ADPLL) for multi-specification generations which takes the SATA Gen1 to SATA Gen3 specifications as a reference material. Besides, the proposed ADSSCG presents a phase compensation technique with a dual phase-rotating approach which improved the drawback of the degraded EMI reduction due to different spread frequency ranges under multiple generation specifications with the same spread ratio. Through the phase-rotating technique, the instantaneous timing error can be effectively compensated, and it shows the ignorable quantization error. Thus, the proposed ADSSCG realized non-dithered fractional division ratios.
This work is designed in a 40 nm standard CMOS process with a supply voltage of 0.9 V. Under the operation frequency of 6 GHz, 3 GHz, and 1.5 GHz, the reduction of EMI is 22.4 dB, 20.5 dB, and 18.8 dB, respectively, with 5000 ppm down spread and 32.89 kHz triangular modulation. The power consumption is 9.74 mW at the highest operation frequency. The full chip area is 0.9 mm2 and the core area is 0.0395 mm2.

關鍵字(中)

★ 電磁干擾
★ 全數位展頻時脈產生器
★ 相位補償

關鍵字(英)

★ Electromagnetic Interference
★ All-Digital Spread-Spectrum Clock Generator
★ Phase Compensation

論文目次

摘要 i
Abstract iii
誌謝 v
目錄 vii
圖目錄 x
表目錄 xiii
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 3
第2章展頻時脈產生器之背景介紹 5
2.1 電磁干擾來源與解決方法 5
2.1.1 電磁干擾 (Electromagnetic Interference, EMI) 5
2.1.2 解決方法 7
2.2 展頻時脈技術理論 9
2.2.1 展頻時脈技術 9
2.2.2 調變波形 11
2.2.3 調變模式 12
2.3 展頻時脈技術探討 13
2.3.1 輸入參考時脈調變技術[16] 14
2.3.2 振盪器之直接調變技術[17] 15
2.3.3 控制多模數除頻器除率之調變技術[25] 16
2.3.4 選擇多相位輸出之調變技術[12] 17
2.3.5 比較與討論 18
第3章具相位補償技術之全數位展頻時脈產生器 19
3.1 簡介 19
3.2 設計流程 20
3.3 電路架構 21
3.4 操作說明 22
3.4.1 全數位式鎖相迴路之操作 22
3.4.2 全數位式展頻時脈產生器之操作 23
3.4.3 相位補償分數除頻器分析 24
3.4.3.1 擾動與非擾動之分數除頻器 24
3.4.3.2 三角波階數分析 26
3.4.3.3 具雙重相位旋轉技巧之相位補償分數除頻器 28
3.5 系統分析 35
3.5.1 全數位式鎖相迴路之S-domain分析 35
3.5.2 電荷幫浦鎖相迴路之S-domain分析 37
3.5.3 計算數位迴路濾波器之參數 39
3.5.4 雜訊分析 43
3.6 行為模擬 46
第4章電路設計考量與整體電路模擬 49
4.1 電路設計與考量 49
4.1.1 相位頻率偵測器 49
4.1.2 時間數位轉換器 51
4.1.3 數位迴路濾波器 55
4.1.4 數位控制振盪器 57
4.1.5 多模數除頻器 61
4.1.6 相位內插器 63
4.1.7 三角波形產生器 65
4.2 模擬結果 67
4.2.1 全數位式鎖相迴路 68
4.2.1.1 佈局前模擬 68
4.2.1.2 佈局後模擬 71
4.2.2 全數位式展頻時脈產生器 73
4.2.2.1 佈局前模擬 73
4.2.2.2 佈局後模擬 74
4.2.3 結果整理 75
4.2.3.1 全數位鎖相迴路 75
4.2.3.2 全數位展頻時脈產生器 77
4.3 規格比較表 78
第5章晶片佈局與量測規劃 81
5.1 電路佈局 81
5.1.1 晶片封裝 83
5.1.2 佈局規劃與電源規劃 85
5.2 量測考量 86
5.2.1 量測環境 86
5.2.2 印刷電路板等效模型 87
5.2.3 高頻輸出緩衝器 88
5.2.4 低頻輸出緩衝器 90
5.2.5 低頻輸入緩衝器 91
第6章結論 93
6.1 結論 93
6.2 未來研究方向 94
參考文獻 95

參考文獻

[1] 洪政亮, “高速有線傳輸系統之時脈產生器關鍵技術,” 博士論文, 國立中央大學, 2014.
[2] VESA DisplayPort Standard Revision 1.2, VESA, Jan 2010.
[3] Serial ATA International Organization: Serial ATA Revision 3.1, SATA-IO, 2011
[4] Universal Serial Bus 3.2 Specification Revision 1.0, USB-IO, 2013
[5] PCI Express® Base Specification Revision 3.0, PCI-SIG, 2010
[6] Y. -H. Kao, and Y. –B. Hsieh, “A fully integrated spread-spectrum clock generator using a dual-path loop filter,” in Proc. IEEE International Midwest Symposium on Circuits and Systems, Aug. 2006, pp. 7–10.
[7] Y. -B. Hsieh, and Y. -H. Kao, “A new spread-spectrum clock generator for SATA using double modulation schemes,” in Proc. IEEE Custom Integrated Circuits Conference, Sept. 2007, pp. 297–300.
[8] Y. -B. Hsieh, and Y. -H. Kao, “A fully integrated spread-spectrum clock generator by using direct VCO modulation,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 7, pp. 1845–1853, Aug. 2008.
[9] C. -Y. Yang, C. -H. Chang, and W. -G. Wong, “A 3.2-GHz down-spread spectrum clock generator using a nested fractional topology,” IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, vol. 91, no. 2, pp. 497–503, Feb. 2008.
[10] C. -Y. Yang, C. -H. Chang, and W. -G. Wong, “A Δ-Σ PLL-based spread spectrum clock generator with a ditherless fractional topology,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 1, pp. 51–59, Jan. 2009.
[11] K. -H. Cheng, C. -L. Hung, and C. -H. Chang, “A 0.77 ps RMS jitter 6-GHz spread-spectrum clock generator using a compensated phase-rotating technique,” IEEE Journal of Solid-State Circuits, vol. 46, no. 5, pp. 1198–1213, May. 2011.
[12] H. Lee, O. Kim, G. Ahn, and D. Jeong, "A low-jitter 5000ppm spread spectrum clock generator for multi-channel SATA transceiver in 0.18um CMOS," IEEE Int. Solid-State Circuits Conference, 2005, pp. 162–163.
[13] F. Pareschi, G. Setti, and R. Rovatti, “A 3-GHz serial ATA spread-spectrum clock generator employing a chaotic PAM modulation,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 10, pp. 2577–2587, Oct. 2010.
[14] S. -G. Bae, G. Kim, and C. Kim, “A 5-GHz sub-sampling PLL based spread-spectrum clock generator by calibrating the frequency deviation” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 10, pp.1132–1136, Oct. 2017.
[15] K. -B. Hardin, J. -T. Fessler, and D. -R. Bush, “Spread spectrum clock generation for the reduction of radiated emissions,” in Proc. IEEE Symposium on Electromagnetic Compatibility, 1994, pp. 227–231.
[16] C. -Y. Lin, T. -J. Wang, and T. -H. Lin, “A 1.5-GHz sub-sampling fractional-N PLL for spread-spectrum clock generator in 0.18-μm CMOS,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2017. pp. 1198–1213.
[17] H. -H. Chang, I. -H. Hua, and S. -I. Liu, "A spread-spectrum clock generator with triangular modulation," IEEE J. Solid-State Circuits, vol.38, no.4, pp. 673–676, Apr. 2003.
[18] C. -H. Wong, and T. -C. Lee, “A 6-GHz self-oscillating spread-spectrum clock generator,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no.5, pp. 1264–1273, May 2013.
[19] K. -H. Cheng, C. -L. Hung, C. -H. Chang, Y. -L. Lo, W. -B. Yang, and J. -W. Miaw, “A spread-spectrum clock generator using fractional-N PLL controlled delta-sigma modulator for Serial-ATA III,” in Proc. IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Apr. 2008, pp. 1–4.
[20] T. Kawamoto, M. Suzuki, and T. Noto, “1.9-ps jitter, 10.0-dBm-EMI reduction spread-spectrum clock generator with autocalibration VCO technique for Serial-ATA application,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 5, pp. 1118–1126, May. 2014.
[21] D. -D. Caro, F. Tessitore, G. Vai, N. Imperato, N. Petra, E. Napoli, C. Parrella, and A. -G. -M. Strollo, “A 3.3 GHz spread-spectrum clock generator supporting discontinuous frequency modulations in 28 nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 50, no. 9, pp. 2074–2089, Sept. 2015.
[22] S. Jang, S. Kim, S. -H. Chu, G. -S. Jeong, Y. Kim, and D. -K. Jeong, “An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation,” in Symposium on VLSI Circuits, Jun. 2015, pp. C136–C137.
[23] I. -T. Lee, S. -H. Ku, and S. -I. Liu, “An all-digital spread-spectrum clock generator with self-calibrated bandwidth,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 10, pp. 2813–2822, Nov. 2013.
[24] D. sheng, C. -C. Chung, and C. -Y. Lee, “A low-power and portable spread spectrum clock generator for SoC applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 6, pp. 1113–1117, Jun. 2011.
[25] S. -Y. Lin, and S. -I. Liu, “A 1.5 GHz all-digital spread spectrum clock generator,” IEEE Journal of Solid-State Circuits, vol. 44, no. 11, pp. 3111–3119, Nov. 2009.
[26] D. -D. Caro, C. -A. Romani, N. Petra, A. -G. -M. Strollo, and C. Parrella, “A 1.27 GHz, all-digital spread spectrum clock generator/synthesizer in 65 nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1048–1060, Mar. 2010.
[27] S. Damphousse, K. Ouici, A. Rizki, and M. Mallinson, “All digital spread spectrum clock generator for EMI reduction,” IEEE Journal of Solid-State Circuits, vol. 42, no. 1, pp. 145–150, Jan. 2007.
[28] N. -D. Dalt, P. Pridnig, and W. Grollitsch, “An all-digital PLL using random modulation for SSC generation in 65nm CMOS,” IEEE International Solid-State Circuits Conference Digest of Technical Papers, Feb. 2013, pp. 252–253.
[29] C. -C. Chung, D. Sheng, and W. -D. Ho, “A low-power and small-area all-digital spread-spectrum clock generator in 65nm CMOS technology,” in Proc. VLSI Design, Automation and Test (VLSI-DAT), April. 2012, pp. 1–4.

[30] C. -C. Chung, D. Sheng, and W. -D. Ho, “A low-cost low-power all-digital spread-spectrum clock generator,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 5, pp. 983–987, May 2015.
[31] T. Sudo, H. Sasaki, N. Masuda, and J. -L. Drewniak, “Electromagnetic interference (EMI) of system-on-package (SOP),” IEEE Transactions on Advanced Packaging, vol. 27, no. 2, pp. 304–314, May 2004.
[32] 花怡慧, “66/133/266MHz展頻時脈產生器之設計與製作,” 碩士論文, 國立台灣大學, 2002.
[33] A. Shoval, W. -M. Snelgrove, and D. -A. Johns, “A 100 Mb/s BiCMOS adaptive pulse-shaping filter,” IEEE Journal on Selected Areas in Communications, vol. 13, pp. 1692–1702, Dec. 1995.
[34] J. Kim, D. -G. Kam, P. -J. Jun, and J. Kim, “Spread spectrum clock generator with delay cell array to reduce the electromagnetic interference,” IEEE Transactions on Electromagnetic Compatibility, vol. 47, no. 4, pp. 908–920, Nov. 2005.
[35] 黃映祥, “具高速相位選擇器之六十億赫茲全數位展頻時脈產生器,” 碩士論文, 國立中央大學, 2013.
[36] V. Kratyuk, P. -K. Hanumolu, U. -K. Moon, and K. Mayaram, “A design procedure for all-digital phase-locked loops based on a charge-pump phase-locked-loop analogy,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 3, pp. 247–251, Mar. 2007.
[37] C. -M. Hsu, M. -Z. Straayer, M. -H. Perrott, “A low-noise wide-BW 3.6-GHz digital ΔΣ fractional-N frequency synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation,” IEEE Journal of Solid-State Circuits, vol. 43, no. 12, pp. 2776–2786, Dec. 2008.
[38] D. -H. Oh, D. -S. Kim, S. Kim, D. -K. Jeong, and W. Kim, “A 2.8Gb/s all-digital CDR with a 10b monotonic DCO,” in Proc. IEEE International Solid-State Circuits Conference. Digest of Technical Papers, Feb. 2007, pp. 222–598.

[39] D. -S. Kim, H. Song, T. Kim, S. Kim, and D. -K. Jeong, “A 0.3–1.4 GHz all-digital fractional-N PLL with adaptive loop gain controller,” IEEE Journal of Solid-State Circuits, vol. 45, no. 11, pp. 2300–2311, Nov. 2010.
[40] H. Song, D. -S. Kim, D. -H. Oh, S. Kim, and D. -K. Jeong, “A 1.0–4.0-Gb/s all-digital CDR with 1.0-ps period resolution DCO and adaptive proportional gain control,” IEEE J. Solid-State Circuits, vol. 46, no. 2, pp. 424–434, Feb. 2011.
[41] B. -W. Garlepp, K. -S. Donnelly, J. Kim, P. -S. Chau, J. -L. Zerbe, C. Huang, C. -V. Tran, C. -L. Portmann, D. Stark, Y. -F. Chan, T. -H. Lee, and M. -A. Horowitz, “A portable digital DLL for high-speed CMOS interface circuits,” IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 632–644, May 1999.

指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2019-8-21

推文