新型加強型氮化鎵高電子遷移率電晶體之電性探討

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姓名

何偉誠(Wei-Cheng Ho) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

新型加強型氮化鎵高電子遷移率電晶體之電性探討

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摘要(中)

本論文針對新型加強型氮化鎵高電子遷移率電晶體(New E-mode GaN HEMT)之元件電性研究進行探討，研究對象為：(1) 加強型氮化鎵高電子遷移率電晶體；(2) 於元件主要閘極與汲極間加入第二閘極，並與源極端相連接之新型加強型氮化鎵高電子遷移率電晶體。實驗結果分別量測不同結構元件的直流電性，並與單閘極結構之加強型氮化鎵高電子遷移率電晶體元件進行比較，預期達成利用第二閘極在導通並且高電流的情況下能抑制其汲極飽和電流(ID,sat)以達到更好的短路能力(short-circuit capability)效果。
實驗流程包含新型加強型氮化鎵高電子遷移率電晶體之元件特性模擬、佈局設計、元件製程以及元件量測；其中，元件模擬使用p-氮化鎵閘極高電子遷移率電晶體(p-GaN gate HEMT)達成加強型(Enhancement-mode)操作，在新結構之第二閘極設計分別為蕭特基接觸(Schottky contact)與金絕半接面(MIS)兩種。透過Silvaco TCAD軟體進行元件之電流特性模擬與基本電性觀察發現蕭特基第二閘極之新結構汲極飽和電流約降為傳統結構之12 %，金絕半第二閘極之新結構汲極飽和電流約降為傳統結構之62 %，導通電阻的上升幅度均在5 %以內。
元件製程方面則將蕭特基第二閘極設計加入至p-氮化鎵閘極高電子遷移率電晶體；金絕半第二閘極設計加入至閘極掘入式加強型氮化鎵金絕半場效電晶體(Recesses-gate E-mode GaN MIS-HEMT)中。量測結果可觀察到，蕭特基第二閘極之新結構汲極飽和電流約降低至單閘極結構的30 %，金絕半第二閘極之新結構汲極飽和電流約降低至單閘極結構的70 %；其中，金絕半第二閘極結構元件之導通電阻上升幅度在6 % 左右，此部分之電性表現與Silvaco TCAD模擬出來之趨勢相同。而亦可從此電性表現來說明透過新結構設計可改善加強型氮化鎵高電子遷移率電晶體在短路能力上之表現。

摘要(英)

In this study, the device characteristics of the new GaN high electron mobility transistor (HEMT) are discussed. The research focus on: (1) Enhancement-mode (E-mode) GaN HEMT; (2) A new type of E-mode GaN HEMT with a second gate between the main gate and the drain which is connected to the source. The experimental results compare the DC characteristics of different second gate E-mode GaN HEMT structure with the single gate E-mode GaN HEMT structure. Second gate structure can suppress the saturation current (ID, sat) under on-state and high current condition and it is expected that by the design of second gate, GaN HEMT can achieve a better short-circuit capability.
The experiment includes device simulation, layout design, device processing, and DC measurement of new GaN HEMT. Device simulation use p-GaN gate HEMT to achieve E-mode operation. The second gate design of the new structure is Schottky contact and MIS contact. Through the Silvaco TCAD simulation, the characteristics show that the Schottky second gate structure reduced ID,sat to about 12% of the single gate structure, the MIS second gate reduced ID,sat to about 62% of the single gate structure, and both of them the on-resistance is increased by less than 5%.
In device processing, the Schottky second gate design is added to the E-mode p-GaN gate HEMT; the MIS second gate design is added to the Recesses-gate E-mode GaN MIS-HEMT. The measurement results show that the Schottky second gate structure is reduced to about 30% of the single gate structure, and the MIS second gate structure is reduced to 70% of the single gate structure; wherein the on-resistance is increased about 6%, and the electrical characteristics of measurement show the same trend as that simulated by Silvaco TCAD. From this electrical characteristics, it can be expected that the new structure design can improve the short circuit capability of GaN HEMT.

關鍵字(中)

★ 加強型
★ 氮化鎵高電子遷移率電晶體
★ 降低汲極飽和電流
★ 第二閘極
★ 短路能力

關鍵字(英)

論文目次

摘要 I
Abstract II
致謝 III
圖目錄 VI
表目錄 XI
第一章緒論 1
1.1 前言 1
1.2 加強型氮化鎵高電子遷移率電晶體發展概況 6
1.3 氮化鎵高電子遷移率電晶體短路能力概況 15
1.4 研究動機與目的 23
1.5 論文架構 25
第二章新型加強型氮化鎵高電子遷移率電晶體設計、模擬與佈局 26
2.1 前言 26
2.2 新型加強型氮化鎵高電子遷移率電晶體設計 26
2.3 加強型氮化鎵高電子遷移率電晶體特性模擬 28
2.3.1 氮化鎵高電子遷移率電晶體元件特性模擬 28
2.3.2 氮化鎵高電子遷移率電晶體以不同設計加入第二閘極之元件特性模擬 31
2.4 結論 39
第三章新型氮化鎵高電子遷移率電晶體元件佈局、製作、量測與電性分析 40
3.1 前言 40
3.2 新型加強型p-氮化鎵閘極高電子遷移率電晶體磊晶設計、元件製程、佈局設計與電性分析 40
3.2.1 磊晶結構 40
3.2.2 材料分析 43
3.2.3 元件製作流程 47
3.2.4 新型加強型p-氮化鎵閘極高電子遷移率電晶體佈局設計 49
3.2.5 新型加強型p-氮化鎵閘極高電子遷移率電晶體電性分析 51
3.3 新型閘極掘入式加強型氮化鎵金絕半場效電晶體佈局設計與電性分析 59
3.3.1 新型閘極掘入式加強型氮化鎵金絕半場效電晶體佈局設計 59
3.3.2 新型閘極掘入式加強型氮化鎵金絕半場效電晶體電性分析 61
3.4 新型空乏型氮化鎵金絕半場效電晶體佈局設計與電性分析 66
3.4.1 新型空乏型氮化鎵金絕半場效電晶體佈局設計 66
3.4.2 新型空乏型氮化鎵金絕半場效電晶體電性分析 68
3.5 結論 72
第四章結論 73
參考文獻 76
附錄 Ⅰ 新型加強型p-氮化鎵閘極高電子遷移率電晶體製程流程 79

參考文獻

[1] Brown, Raphael, “A novel AlGaN/GaN based enhancement-mode high electron mobility transistor with sub-critical barrier thickness,” Phd thesis, University of Glasgow, July 2015.
[2] Xiaofeng Ding, Yang Zhou, and Jiawei Cheng, “A Review of Gallium Nitride Power Device and Its Applications in Motor Drive,” IEEE CES Transactions on Electrical Machines and Systems, vol. 3, no. 1, pp. 54-64, Mar. 2019.
[3] O. Ambacher, J. Smart, J. R. Shealy, N. G. Weimann, K. Chu, M. Murphy, W. J. Schaff, and L. F. Eastman, “Two-dimensional electron gases induced by spontaneous and piezoelectric polarization charges in N- and Ga-face AlGaN/GaN heterostructures,” Journal of Applied Physics., vol. 85, no. 6, pp. 3222–3233, Mar. 1999.
[4] D. Balaz, “Current Collapse and Device Degradation in AlGaN/GaN Heterostructure Field Effect Transistors,” University of Glasgow, 2010.
[5] W. Saito, Y. Takada, M. Kuraguchi, K. Tsuda, and I. Omura, “Recessed-Gate Structure Approach Toward Normally Off High-Voltage AlGaN/GaN HEMT for Power Electronics Applications,” IEEE Transactions Electron Devices, Vol. 53, No. 2, pp. 356-362, Feb. 2006.
[6] Kevin J. Chen, L. Yuan, M. J. Wang, H. Chen, S. Huang, Q. Zhou, C. Zhou, B. K. Li, and J. N. Wang, “Physics of fluorine plasma ion implantation for GaN normally off HEMT technology,” IEEE IEDM, pp. 19.4.1-19.4.4, Dec. 2011.
[7] Ki-Sik Im, Ryun-Hwi Kim, Ki-Won Kim, Dong-Seok Kim, Chun Sung Lee, Sorin Cristoloveanu, and Jung-Hee Lee, “Normally Off Single-Nanoribbon Al2O3/GaN MISFET, ” IEEE Electron Device Letters, vol. 34, no. 1, pp.27–29, Jan. 2013.
[8] H Amano et al., “The 2018 GaN power electronics roadmap,” IOP Journal of Physics D: Applied Physics, vol. 51, no. 16, Mar. 2018.
[9] Matteo Meneghini, Oliver Hilt, Joachim Wuerﬂ and Gaudenzio Meneghesso, “Technology and Reliability of Normally-Off GaN HEMTs with p-Type Gate,” Energies, Jan. 2017.
[10] Giuseppe Greco, Ferdinando Iucolano, Fabrizio Roccaforte, “Review of technology for normally-oﬀ HEMTs with p-GaN gate,” Materials Science in Semiconductor Processing, vol. 78, pp. 96-106, May 2018.
[11] Yasuhiro Uemoto, Masahiro Hikita, Hiroaki Ueno, Hisayoshi Matsuo, Hidetoshi Ishida, Manabu Yanagihara, Tetsuzo Ueda, Tsuyoshi Tanaka and Daisuke Ueda, “Gate Injection Transistor (GIT)—A Normally-Off AlGaN/GaN Power Transistor Using Conductivity Modulation,” IEEE Transactions on Electron Devices, vol. 54, no. 12, pp. 3393-3399, Dec. 2007.
[12] Saichiro Kaneko, Masayuki Kuroda, Manabu Yanagihara, Ayanori Ikoshi, Hideyuki Okita, Tatsuo Morita, Kenichiro Tanaka, Masahiro Hikita, Yasuhiro Uemoto, Satoru Takahashi and Tetsuzo Ueda, “Current-collapse-free operations up to 850 V by GaN-GIT utilizing hole injection from drain,” 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC’s (ISPSD), May 2015.
[13] Hideyuki Okita, Masahiro Hikita, Akihiko Nishio, Takahiro Sato, Keiichi Matsunaga, Hisayoshi Matsuo, Masaya Mannoh and Yasuhiro Uemoto, “Through Recessed and Regrowth Gate Technology for Realizing Process Stability of GaN-GITs,” 2016 IEEE 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Jun. 2016.
[14] Injun Hwang, Jongseob Kim, Hyuk Soon Choi, Hyoji Choi, Jaewon Lee, Kyung Yeon Kim, Jong-Bong Park, Jae Cheol Lee, Jongbong Ha, Jaejoon Oh, Jaikwang Shin, and U-In Chung, “p-GaN Gate HEMTs With Tungsten Gate Metal for High Threshold Voltage and Low Gate Current,” IEEE Electron Device Letters, vol. 34, no. 2, pp. 202-204, Feb. 2013.
[15] Finella Lee, Liang-Yu Su, Chih-Hao Wang, Yuh-Renn Wu, and Jianjang Huang, “Impact of Gate Metal on the Performance of p-GaN/AlGaN/GaN High Electron Mobility Transistors,” IEEE Electron Device Letters, vol. 36, no. 3, pp. 232-234, Mar. 2015.
[16] Yuan Lin, Yueh Chin Lin, Franky Lumbantoruan, Chang Fu Dee, Burhanuddin Yeop Majilis, and Edward Yi Chang, “A Novel Digital Etch Technique for p-GaN Gate HEMT,” 2018 IEEE International Conference on Semiconductor Electronics (ICSE), Aug. 2018.
[17] 簡潔, “600-V溝渠式絕緣閘雙極性電晶體設計、分析與短路能力探討,” 國立中央大學電機工程學系碩士論文, 2013.
[18] M. Fernández, X. Perpiñà, J. Roig, M. Vellvehi, F. Bauwens, X. Jordà, and M. Tack, “P-GaN HEMTs Drain and Gate Current Analysis Under Short-Circuit,” IEEE Electron Device Letters, vol. 38, no. 4, pp. 505-508, Apr. 2017.
[19] He Li, Xiao Li, Xiaodan Wang, Jin Wang, Yazan Alsmadi, Liming Liu, and Sandeep Bala, “E-mode GaN HEMT Short Circuit Robustness and Degradation,” 2017 IEEE Energy Conversion Congress and Exposition (ECCE), Oct. 2017.
[20] M. Fernández, X. Perpiñá, M. Vellvehi, X. Jordà, J. Roig, F. Bauwens, and M. Tack, ” Short-Circuit Capability in p-GaN HEMTs and GaN MISHEMTs,” 2017 29th International Symposium on Power Semiconductor Devices and IC′s (ISPSD), Jun. 2017
[21] Youngshin Eum, Kazuhiro Oyama, Nobuyuki Otake, and Shinichi Hoshi, “Highly reliable GaN MOS-HFET with high short-circuit capability,” 2017 29th International Symposium on Power Semiconductor Devices and IC′s (ISPSD), Jun. 2017.
[22] Taifang Wang, Jun Ma, and Elison Matioli. “1100 V AlGaN GaN MOSHEMTs With Integrated Tri-Anode Freewheeling Diodes,” IEEE Electron Device Letters, vol.39, no.7, pp. 1038-1041, Jul. 2018.
[23] O. Hilt, A. Knauer, F. Brunner, E. Bahat-Treidel and J. Würfl, ” Normally-off AlGaN/GaN HFET with p-type GaN Gate and AlGaN Buffer,” 2010 22nd International Symposium on Power Semiconductor Devices & IC’s (ISPSD), Jun. 2010.
[24] Liang-Yu Su, Finella Lee, and Jian Jang Huang, “Enhancement-Mode GaN-Based High-Electron Mobility Transistors on the Si Substrate With a P-Type GaN Cap Layer,” IEEE Transactions on Electron Devices, vol. 61, no. 2, pp.460–464, Feb. 2014.
[25] 余翊瑄, “氮化鎵電晶體SPICE模型建立與反向導通特性分析,” 國立中央大學電機工程學系碩士論文, 2019.

指導教授

辛裕明(Yue-Ming Hsin)

審核日期

2019-8-22

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