適用於陸規DTTB之可組態QC-LDPC
解碼硬體架構設計

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姓名

溫品涵(Pin-han Wen) 查詢紙本館藏

畢業系所

通訊工程學系

論文名稱

適用於陸規DTTB之可組態QC-LDPC 解碼硬體架構設計
(A Configurable Hardware Architecture of Decoder for China’s DTTB QC-LDPC Code )

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摘要(中)

陸規DTTB以QC-LDPC作通道編碼，本論文利用校驗矩陣以區塊為單位的分佈特性，設計區塊平行處理，並將校驗矩陣的區塊特性儲存於記憶體，以FPGA實現區塊式掃描演算法作為解碼，故調整記憶體中的矩陣特性，即可以此架構使用regular-LDPC的各種碼率或規格的解碼。
　　本論文提出之可組態的解碼架構，在不降低傳輸效率(Throughput)的情況下，除了節省記憶體的使用程度，同時也降低硬體資源。

摘要(英)

More and more broadband broadcasting systems, like 802.11e, 802.11n and China’s DTTB, use multi-rate QC-LDPC codes as their channel coding schemes to support the flexibility in code rate and code length. In this thesis, I present a decoder for multi-rate QC-LDPC codes in China’s DTTB system. The Modified Min-Sum Algorithm, which is adequate to the hardware structure, is used to reduce the complexity of the LDPC decoder while keeping almost the same performance. In the proposed architecture, the decoder can be easily reconfigured for multi-rate or multi-standard as long as the QC-LDPC code is characterized by a base matrix with circular-rotation index. Moreover, the FPGA implementation of this partially paralleled decoder is demonstrated to be more efficient in terms of slices and memory blocks without sacrificing in data throughput.

關鍵字(中)

★ 線性區塊碼
★ LDPC
★ QC-LDPC
★ 陸規DTTB
★ 最小和積演算法

關鍵字(英)

★ LDPC
★ QC-LDPC
★ Sum-Product
★ Minimum-Sum
★ China's DTTB
★ FPGA
★ Block Code

論文目次

中文摘要 ................................................................................................................................................. I
Abstract ................................................................................................................................................... II
圖目錄 .............................................................................................................................................. VI
表目錄 ........................................................................................................................................... VIII
第一章緒論 .................................................................................................................................. 1
1.1 動機 .................................................................................................................................. 1
1.2 論文組織 ......................................................................................................................... 1
第二章 LDPC Code ...................................................................................................................... 2
2.1 Block Code ..................................................................................................................... 2
2.2 LDPC 碼定義 ................................................................................................................. 4
2.3 Tanner Graph ................................................................................................................ 5
2.4 LDPC 碼解碼 ................................................................................................................. 6
2.4.1 Sum Product Algorithm ............................................................................. 6
2.4.2 Modified Minimum Sum Algorithm ................................................... 11
第三章軟體模擬LDPC 碼 ................................................................................................... 14
3.1 量化分析 ...................................................................................................................... 14
3.2 疊帶次數分析 ............................................................................................................ 15
第四章 FPGA 實現LDPC 碼解碼架構 ............................................................................ 19
4.1 QC‐LDPC 碼解碼架構設計 ................................................................................... 19
4.1.1 Modified Minimum Sum Algorithm ....................................................... 21
4.1.2 區塊式掃描演算法 .................................................................................... 22
4.1.3 區塊式掃描架構 ......................................................................................... 27
4.1.4 掃描式架構流程 ......................................................................................... 28
4.2 記憶體設計 ................................................................................................................. 31
4.2.1 定義控制核心記憶體A‐RAM ............................................................... 31
4.2.2 平行讀寫I‐RAM ......................................................................................... 34
4.2.3 平行讀寫Dual Port Rcv‐RAM .............................................................. 37
4.2.4 平行讀寫Dual Port S‐RAM ................................................................... 40
4.2.5 記憶體使用率 .............................................................................................. 42
4.3 核心運算單元 ............................................................................................................ 43
4.3.1 循環位移

參考文獻

[1] R. M. Tanner, “A recursive approach to low complexity codes,” IEEE Trans. Inform. Theory, vol. 74, no. 2, pp. 533-547, Sept. 1981.
[2] F. R. Kschischang, B. J. Frey, and H. A. Loeliger, “Factor graphs and the sum-product algorithm,” IEEE Trans. Inf. Theory, vol. 47, pp. 498–519, Feb. 2001.
[3] L. Zhang, L. Gui, Y. Xu, and W. Zhang, "Configurable multi-rate decoder architecture for QC-LDPC codes based broadband broadcasting system," IEEE Trans. on Broadcasting, vol. 54, pp. 226-235, June 2008.
[4] L. Yang, H. Liu, and C.J. Shi, "Code construction and FPGA implementation of a low-error-floor multi-rate low-density parity-check code decoder," IEEE Trans. on Circuits and Systems-I, vol. 53, pp. 892-904, April 2006.
[5] Z. Wang and Z. Cui, "A memory efficient partially parallel decoder architecture for quasi-cyclic LDPC codes," IEEE Trans. on VLSI Systems, vol. 15, pp. 483-488, April 2007.
[6] T. Zhang and K.K. Parhi, "Joint (3,k)-regular LDPC code and decoder/encoder design," IEEE Trans. on Signal Processing, vol. 52, pp. 1065-1079, April 2004.
[7] J. Zhao, F. Zarkeshvari, and A.H. Banihashemi, "On the implementation of mini-sum algorithm and its modifications for decoding low-density parity-check codes," IEEE Trans. on Communications, vol. 53, pp. 549-554, April 2005.
[8] D. Oh and K.K. Parhi, "Area efficient controller design of barrel shifters for reconfigurable LDPC decoders," IEEE International Symposium on Circuits and Systems, pp. 240-244, May 2008.
[9] Yih-Min Chen and Pin-Han Wen, “Design and FPGA Implementation of a Configurable Multi-Rate QC-LDPC Decoder with Raster Scanning Architecture” (submitted)

指導教授

陳逸民(Yih-min Chen)

審核日期

2009-7-22

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