以分段線性表實現基於波動數位濾波器之電路仿真器

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姓名

洪思芸(Si-Yun Hong) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

以分段線性表實現基於波動數位濾波器之電路仿真器
(Hardware Implementation of WDF-Based Circuit Emulators Using Piecewise Linear Tables)

相關論文

★ 用於類比電路仿真之波動數位濾波器架構的自動建構方法	★ 使用波動數位濾波器與非線性MOS模型的類比電路模擬平台
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★ 用於類比電路仿真器的波動數位濾波器之硬體最佳化方法	★ 自動辨識混合訊號電路中構成區塊及RLC元件之方法

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摘要(中)

隨著製程技術發展日新月異，超大型積體電路設計愈來愈複雜，單晶片系統( System on Chip , SOC )儼然已成為設計的主流。一個SOC設計當中通常同時包含數位電路與類比電路，所以如何整合與驗證類比/混合訊號(Analog/mixed-signal, AMS)電路將會是一個很大的挑戰，特別是類比電路的部分。數位電路已經有了完整的驗證方法與仿真的平台，然而目前仍缺乏成熟的類比電路仿真器，可以解決混訊驗證的問題。本篇論文中，我們採用波動數位濾波器(Wave Digital Filter, WDF)的原理，將類比電路轉換成對應的數位電路，以達成在FPGA上與數位電路一起模擬的目標。
本篇根據之前關於WDF電路仿真的流程，開發了具備動態輸入的混訊電路硬體實現流程，這樣的FPGA硬體實現流程，可以讓整個仿真流程更真實更完整。關於非線性的MOS元件，本論文將原本的查表法，利用分段線性(Piecewise Linear)方法簡化，透過記錄轉折點及斜率，減少了實現表格所需的硬體資源，同時我們也修改了先前的硬體架構，減少FPGA在軟體與硬體間溝通的次數，提高了硬體的吞吐量(Throughput)，加快了仿真的速度。由實驗結果顯示，本篇論文所提出的硬體實現流程可以有效提升波動數位濾波器的硬體仿真效率。

摘要(英)

With the rapid development of process technology, the design of Very-Large-Scale Integration (VLSI) circuits becomes more and more complex. System-on-Chip (SOC) has become the main stream of VLSI design. Because SOC designs usually consist of both analog and digital circuits, there are big challenges for system integration and verification of Analog/Mixed-Signal (AMS) circuits, especially for analog circuits. Digital circuits already have a complete verification and simulation platform, but there is no mature emulator for analog circuits to solve the problem of mixed-signal verification. In this thesis, we adopt Wave Digital Filter(WDF) theorem to convert analog circuits into corresponding digital circuits. It allows analog circuits to be emulated with digital circuits on the same FPGA.
Based on the relevant research of WDF emulation process, this thesis develops the hardware implementation flow of the mixed signal circuits with dynamic inputs. This FPGA implementation flow makes the entire emulation process complete in real applications. About the non-linear MOS components, this thesis uses the Piecewise Linear method to reduce the size of look-up tables dramatically. By recording points and slopes, we reduce the required hardware to implement the tables and still keep the emulation accuracy. We also modify the hardware architecture in previous works to reduce the communication overhead between software and hardware in FPGA. It improves the throughput and accelerates the emulation speed. The experimental results show that the simplified hardware implementation flow can greatly improve the efficiency of analog circuit emulation based on wave digital filters.

關鍵字(中)

★ 數位濾波器
★ 分段線性法
★ 預測法

關鍵字(英)

★ Wave Digital Filter
★ Piece-wise linear
★ Forcasting

論文目次

摘要 i
Abstract vi
致謝 vii
目錄 viii
圖目錄 x
表目錄 xiii
1 第一章、緒論 1
1-1 前言 1
1-2 相關研究 3
1-2-1 場列式可程式類比陣列(FPAA) 3
1-2-2 可程式化類比元件陣列(PANDA) 5
1-2-3 基於波動數位濾波器(WDF)的電路仿真 7
1-3 研究動機與問題定義 7
1-4 論文結構 8
2 第二章、背景知識 10
2-1 數位濾波器(Digital Filter)模型 10
2-2 波動數位濾波器(Wave Digital Filter) 12
2-2-1 波動數位濾波器模型 12
2-2-2 配線器(Adaptor) 15
2-2-3 非線性半導體場效電晶體模型(MOSFET) 20
2-2-4 基於敏感度的WDF運算方法 22
3 第三章、WDF表格縮減技術與硬體實作 23
3-1 WDF配線器(Adaptor)實現流程 24
3-1-1 串並聯配線器計算方法 25
3-1-2 J型配線器(J-type adaptor)阻抗值預測 27
3-1-3 計算J型配線器Gamma值 30
3-1-4 執行WDF配線器實例 31
3-2 基於分段線性法表格縮減技術 33
3-3 WDF硬體實作優化與實現 37
3-3-1 硬體實現平台 37
3-3-2 WDF硬體資料溝通技術 38
3-3-3 動態輸入於混訊電路仿真流程 40
4 第四章、實驗結果 43
4-1 實驗環境 43
4-2 反向放大器(Inverting Amplifier) 43
4-3 共源極放大器(Common-Source Amplifier) 45
4-4 施密特觸發器電路(Schmitt trigger) 48
4-5 生醫心跳感測模擬電路 51
5 第五章、結論 55
6 參考文獻 56

參考文獻

[1] A. V. Karthik and J. Roychowdhury, "ABCD-L: Approximating continuous linear systems using Boolean models," in Proceedings of the 50th Annual Design Automation Conference, pp. 1–9, May 2013.
[2] R. A. Rutenbar, "Design automation for analog: The next generation of tool challenges," Proceedings of IEEE/ACM International Conference, pp. 458–460, Nov. 2009.
[3] M. Vertregt, “The analog challenge of nanometer CMOS,” Int’l Electron Devices Meeting, pp.1-8, Dec. 2006
[4] W. Wu, Y.-L. Chen, Y. Ma, C.-N. Liu, J.-Y. Jou, S. Pamarti, and L. He, “Wave Digital Filter based analog circuit emulation on FPGA,” IEEE Int’l Symp. on Circuit and Systems, May 2016.
[5] Fettweis, “Wave digital filters: Theory and practice,” Proceedings of the IEEE, vol. 74, no. 2, pp. 270–327, 1986.
[6] K. Meerkotter and R. Scholz, “Digital simulation of nonlinear circuits by wave digital filter principles,” IEEE Int’l Symp. on Circuits and Systems, pp. 720–723, 1989.
[7] H. Kutuk and S.-M. Kang, “A field-programmable analog array (FPAA) using switched-capacitor techniques,” in Proc. IEEE Int’l Symp. on Circuits and Systems, vol. 4, 1996, pp. 41-44, 1996.
[8] E. K. Lee and W. L. Hui, “A novel switched-capacitor based field-programmable analog array architecture,” in Field-Programmable Analog Arrays, Springer, pp. 33-50, 1998.
[9] E. K. Lee and P. G. Gulak, “A transconductor-based field-programmable analog array,” in Proc. IEEE Int’l Solid-State Circuits Conf., pp. 198-199, 1995.
[10] B. Pankiewicz, M. Wojcikowski, S. Szczepanski, and Y. Sun, “A field programmable analog array for CMOS continuous-time OTA-C filter applications,” IEEE J. Solid-State Circuits, vol. 37, no. 2, pp. 125-136, 2002.
[11] T. S. Hall, C. M. Twigg, J. D. Gray, P. Hasler, and D. V. Anderson, “Large-scale field-programmable analog arrays for analog signal processing,” IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 52, no. 11, pp. 2298-2307, 2005.
[12] N. Suda & J. Suh & N. Hakim & Y. Cao & B. Bakkaloglu, “A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation,” IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 181-190, Jan 2016.
[13] S.-Y. Pan, "A new adaptor for WDF-based analog emulator with complicated topology," National Central University, Taiwan, 2017.
[14] C.-H. Wang, “Nonlinear Transistor Model for WDF-Based Analog Emulators,” National Central University, Taiwan, 2016.
[15] Shatkay, H., Zdonik, S. B, “Approximate queries and representations for large data sequences,” Proceedings of the Twelfth International Conference on, New Orleans, LA, pp. 536-545, 1996.
[16] M.-L. Li, " Resource optimization for hardware generation of WDF-based circuit emulators" National Central University, Taiwan, 2019
[17] J-X Tsai “On WDF Structure Synthesis and Simulation for Analog Circuit Emulation,” National Central University, Taiwan, 2019
[18] H-Y Chang, “On Table Reduction for WDF based Analog Circuit Emulation on FPGA,” National Central University, Taiwan, 2018
[19] Y.-S. Han, “A simulation platform for analog circuits using wave digital filters and nonlinear MOS model,” National Central University, Taiwan, 2015.
[20] H.-P. Yang, “Automatic construction and scheduling of the Wave Digital Filter structures for analog emulators,” National Central University, Taiwan, 2016.
[21] W. Wu, Y.-L. Chen, Y. Ma, C.-N. Liu, J.-Y. Jou, S. Pamarti, and L. He, “Wave Digital Filter based analog circuit emulation on FPGA,” IEEE Int’l Symp. on Circuit and Systems, May 2016.
[22] B. J. Sheu, D. L. Scharfetter, P.-K. Ko, and M.-C. Jeng, “Bsim: Berkeley short-channel IGFET model for MOS transistors,” IEEE J. Solid-State Circuits, vol. 22, no. 4, pp. 558–566, 1987.
[23] T. Shima, T. Sugawara, S. Moriyama, and H. Yamada, “Three-dimensional table look-up MOSFET model for precise circuit simulation,” IEEE J. Solid-State Circuits, vol. 17, no. 3, pp. 449-454, 1982.
[24] Xilinx, Inc., “Zynq-7000 All programmable SoC overview,” 2016 [Online].Available:https://www.xilinx.com/support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf

指導教授

周景揚(Jing-Yang Jou)

審核日期

2020-8-17

推文