一個寬電壓操作範圍使用振盪器增益校正技術之全數位展頻時脈產生器

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姓名

曾御翔(Yu-Hsiang Tseng) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

一個寬電壓操作範圍使用振盪器增益校正技術之全數位展頻時脈產生器
(A Wide-Supply-Voltage-Range All Digital Spread-Spectrum Clock Generator With the DCO Gain Calibration Technique)

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摘要(中)

本論文提出一個應用於 SATA-I/SATA-II 規格的全數位展頻時脈產生器（ADSSCG），全數位展頻時脈產生器由鎖相迴路（PLL）與展頻控制電路所組成，展頻控制電路採用直接調變數位控制振盪器（DM-DCO）實現真實小數除數，並降低量化雜訊。振盪器增益校正電路以全數位實現，可以抵抗製程、電壓與溫度的變異(anti-PVT-variation)，因此在 0.75（0.6 V）、1.5（0.7 V）和 3 GHz（1 V）的操作頻率下皆能實現 5000 ppm 的向下展頻量。當展頻模式啟動時，鎖相迴路使用開迴路以降低功率消耗。本論文中還提出一個應用於振盪器的高解析度電晶體變容器。展頻時脈產生器以全數位設計，因此可以擁有較寬的操作電壓範圍。
全數位展頻時脈產生器採用 TSMC 90 nm MSG 1P9M CMOS 製程實現，鎖相迴路可操作在 0.6 V 至 1.3 V 的電源電壓範圍。整體晶片與核心電路面積分別為 730 × 805 μm 2 與 162 × 238 μm 2。當全數位展頻時脈產生器操作在 1.5 GHz（0.7 V）時，所測得的電磁干擾抑制量為 11.15 dB，未開啟與開啟展頻模式的均方根抖動分別為 2.23 ps 與 2.35 ps，對於應用於 SATA-I 之規格，全數位展頻時脈產生器可在 0.7 至 1.1 V 的電源電壓範圍內提供 1.5 GHz 的操作頻率。當全數位展頻時脈產生器操作在 3 GHz（1 V）時，測得的電磁干擾抑制量為14.23 dB，未開啟與開啟展頻模式的均方根抖動分別為 0.94 ps 和 1.02 ps，對於應用於 SATA-II 之規格，全數位展頻時脈產生器可以在 1.0 至 1.3 V 的電源電壓範圍內提供 3 GHz 的操作頻率。操作在 0.75 GHz 時的最低電源電壓為 0.6 V，測得的電磁干擾抑制量為 9.59 dB，未開啟與開啟展頻模式的均方根抖動分別為 4.12 ps 和 4.74 ps。展頻模式在 0.75（0.6 V）、1.5（0.7 V）和 3 GHz（1 V）下的功率消耗分別為 0.32、0.67 和 2.22 mW。因此，本論文之全數位展頻時脈產生器適合應用於寬範圍操作電壓之系統與 SATA-I/SATA-II 之規格。

摘要(英)

This thesis proposes an all-digital spread spectrum clock generator (ADSSCG) for SATA-I/SATA-II applications. The ADSSCG consists of a phase-locked loop (PLL) and a spread spectrum scheme. The spread spectrum control circuit uses direct modulation digital controlled oscillator (DM-DCO) to achieve fractional frequency division ratios and reduce quantization noise. The DCO’s digital gain corrector has an automatic calibration scheme under process, voltage and temperature variations. Therefore, it can achieve a down-spread frequency of 5000 ppm at operating frequencies of 0.75 (at 0.6 V), 1.5 (at 0.7 V) and 3 GHz (at 1 V). When the spread spectrum mode is activated, this PLL adopted an opened loop scheme for low power consumption. This thesis also introduces a high-resolution transistor varactor for DCO. The digital type ADSSCG scheme is easy to obtain a wider power supply voltage working range.
This ADSSCG is implemented with TSMC 90 nm MSG 1P9M CMOS process, and the PLL can operate within a power supply voltage range of 0.6 V to 1.3 V. The test chip and core areas are 730 × 805 μm2 and 162 × 238 μm2, respectively. When the ADSSCG is running at 1.5 GHz (0.7 V) operating frequency, the measured EMI is reduced by 11.15 dB. The RMS jitters with and without the spread spectrum mode are 2.35 ps and 2.23 ps, respectively. For SATA-I application, the ADSSCG can provide an operating frequency of 1.5 GHz within a power supply voltage range of 0.7 to 1.1 V. When the ADSSCG is running at 3 GHz (3 V) operating frequency, the measured EMI is reduced by 14.23 dB. The RMS jitters with and without the spread spectrum mode are 1.02 ps and 0.94 ps, respectively. For SATA-II application, the ADSSCG can provide an operating frequency of 3 GHz within a power supply voltage range of 1.0 to 1.3 V. For the lowest power supply voltage of 0.6 V at 0.75 GHz, the measured EMI is reduced by 9.59 dB. The RMS jitters with and without the spread spectrum mode are 4.74 ps and 4.12 ps, respectively. The power consumptions of spread spectrum mode at 0.75 (at 0.6 V), 1.5 (at 0.7 V) and 3 GHz (at 1 V) are 0.32, 0.67 and 2.22 mW, respectively. Therefore, this ADSSCG is suitable for wide power supply voltage range system and SATA-I/SATA-II applications.

關鍵字(中)

★ 展頻時脈產生器
★ 全數位式鎖相迴路

關鍵字(英)

★ Spread-spectrum clock generator
★ All-digital phase locked loop

論文目次

摘要 I
Abstracts III
目錄 V
圖目錄 VIII
表目錄 XI
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 1
第2章展頻時脈產生器之背景介紹 2
2.1 電磁干擾來源與解決方法 2
2.1.1 屏蔽技術(Shielding)[1] 2
2.1.2 差動時脈技術(Different clocking)[2] 3
2.1.3 脈波重整濾波器技術(Pulse shaping filter)[3] 4
2.1.4 展頻時脈產生器技術(Spread spectrum clock generator)[4] 4
2.2 展頻時脈產生器架構探討 7
2.2.1 輸入參考時脈調變技術[5] 8
2.2.2 振盪器之直接調變技術[6] 9
2.2.3 利用多模數除頻器之除率調變技術[7] 10
2.2.4 選擇多相位輸出之調變技術[8] 12
2.2.5 文獻之比較 13
第3章全數位鎖相迴路系統分析 14
3.1 鎖相迴路系統分析 14
3.1.1 電荷幫浦鎖相迴路S平面分析 14
3.1.2 使用時間數位轉換器之全數位鎖相迴路S平面分析 17
3.1.3 使用二位元Bang-bang相位偵測器之全數位鎖相迴路S平面分析 17
3.1.4 數位迴路濾波器線性模型 18
3.2 全數位鎖相迴路濾波器參數計算 19
3.2.1 使用時間數位轉換器的全數位鎖相迴路參數計算 20
3.2.2 使用二位元Bang-bang相位偵測器的全數位鎖相迴路參數計算 21
3.3 參數設計 22
3.4 行為模擬 23
第4章一個直接調變振盪器與校正振盪器增益之3-GHz全數位展頻時脈產生器 25
4.1 簡介 25
4.2 設計流程 26
4.3 電路架構 27
4.4 操作說明與子電路介紹 27
4.4.1 全數位式鎖相迴路之操作 28
4.4.2 展頻三角波階數分析 30
4.4.3 高解析度數位控制變容器 32
4.4.4 數位控制振盪器 34
4.4.5 振盪器展頻解析度校正電路之操作 37
4.4.6 除法運算電路 38
4.4.7 全數位式展頻時脈產生器之操作 41
4.4.8 二位元Bang-bang相位偵測器 41
4.4.9 數位迴路濾波器 43
第5章整體電路模擬 45
5.1 電路佈局前模擬 45
5.2 電路佈局 48
5.3 晶片封裝 49
5.4 電路佈局後模擬 50
第6章晶片佈局與量測 52
6.1 晶片照相與量測環境設定 52
6.2 量測結果 54
6.3 量測結果總結 60
第7章結論與未來研究方向 63
7.1 結論 63
7.2 未來研究方向 64
參考文獻 65

參考文獻

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2021-9-6

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