| 摘要(英) |
Ka band (26.5--40 GHz) is currently the frequency band used by the fifth generation of mobile communications. This frequency band has a large bandwidth and is usually used in satellite communications. The 35-GHz cloud radar is also one of the applications in the millimeter wave frequency band. Whether it is the fifth-generation mobile communications or radar systems, phased arrays are an indispensable character in this frequency band. The phase shifter is one of the most critical circuits in the phase array, and the main function can be used to provide an adjustable phase difference. If the phase difference between the antennas in the phased array is controlled, the direction of transmitting and receiving in the phased array can be changed. In this thesis, we use two processes to achieve Ka-band passive phase shifters, namely TSMC 90-nm CMOS process and TSMC 0.18 um CMOS process, and we use TSMC 90-nm CMOS process to achieve a 35-GHz digitally controlled variable gain amplifier.
In Chapter 2, we use the TSMC 90-nm CMOS process to design a Ka-band 4-bit passive phase shifter. The operating frequency of the circuit is 35 GHz. The 22.5°, 45° and 90° phase shifter use transmission line-based all-pass network architecture, and the 180° phase shifter uses two stages of transmission line-based all-pass network with different center frequencies. The network is connected in series, and the center frequencies are 25 GHz (LB) and 50 GHz (HB). The measurement results show that the phase shift of all states tends to increase and shift to high frequency, and the root mean square phase error also rises to 22.96°. Therefore, we redefine the bandwidth as the Ka band. In the Ka band, the return loss is greater than 8.51 dB, the insertion loss rises to 20.1 dB, and the amplitude error is within ± 1.73 dB.
In order to improve the measurement results to resimulate, we mainly use two methods. The first is for electrical length of the actual transmission line that is shorter than expected, so we reduce the dielectric constant of the stack. Using the second method because We can′t confirm the dielectric constant as the main reason.
We guess that the parasitic inductance on the MIM capacitor model is less than the actual one. Therefore, we series inductor next to the MIM capacitor to make sure that the parasitic inductance of the model is not too different from the actual parasitic inductance. Both of methods can make the simulation results close to the measurement results.
In Chapter 3, we use TSMC 90-nm CMOS process to design a Ka-band 90°
phase shifter. The operating frequency of the circuit is 35 GHz and the circuit architecture uses a transmission line-based all-pass network. We design the circuit which is mentioned in section 2.6 to resimulate (turn down the dielectric constant of the stack). In section 2.6, we turn down the dielectric constant of the stack so that the electrical length of the transmission line can be close to the actual electrical length. We turn down the dielectric constant by 15% to make the phase shift close to the measurement result, and we capture the 90°
phase shifter to redesign it. We fine-tune the capacitance value so that the phase error can be Within 3°
. The measurement results show that when the phase error is less than 3°
, the relative bandwidth can reach 28.8% (33.6-44.9 GHz). Within the bandwidth, the return loss is greater than 12.25 dB, the insertion loss is less than 5.09 dB, and the amplitude error is within ±0.36 dB.
We guess in Section 2.6 that the actual electrical length of the transmission line will be shorter than expected, so we turn down the dielectric constant of the stack for resimulation. But we can′t confirm that the dielectric constant is the main reason. Therefore, when we redesign the circuit, we will design the transmission line test key. The simulation results and measurement results of the transmission line show that the electrical length of the measurement result will be shorter than the electrical length of the simulation result, so it can be verified that the inference in section 2.6 is correct.
In Chapter 4, we use TSMC 0.18 um CMOS process to realize the circuit that uses the TSMC 90-nm CMOS process in Chapter 3.Although the performance of using TSMC 0.18 um CMOS process at 35-GHz will be poor, the cost of using TSMC 0.18 um CMOS process can be relatively low.The circuit of the former laboratory master [25] is digital 4-bit phase shifter using transmission line-based all-pass network. We can see that the measurement result is very different from the simulation result in this circuit, so we capture the 90° phase shifter of this circuit and resimulated it to make the simulation result close to the measurement result.
Then we guess that the reason for the phase shift has a tendency to become smaller and shift to high frequency. It may be that the parasitic inductance of the MIM capacitor model originally provided by the T18 process is estimated to be larger than the actual one. Therefore, we series a negative ideal inductance next to the MIM capacitor to make the parasitic inductance of the MIM capacitor buckle back. After we add the inductance to make the phase shift close to the measurement result, we redesign the 90° phase shifter, we fine-tune the capacitance value so that the phase error can be Within 3°. The measurement results show that when the phase error is less than 3°, the relative bandwidth can reach 22.58% (33-41.4 GHz). Within the bandwidth, the return loss is greater than 13.9 dB, the insertion loss is less than 5.9 dB, and the amplitude error is within ±0.44 dB.
We guess in Section 4.2 that the actual electrical length of the transmission line will be shorter than expected, so we turn down the dielectric constant of the stack for resimulation. But we can′t confirm whether the inference in Section 4.2 is one of the reasons. Therefore, when we redesign the circuit, we will design two transmission line test keys. The simulation results and measurement results of the transmission line show that the electrical length of the measurement is shorter than that of the simulation. Therefore, it can be verified that the inference in section 4.2 electrical length is correct.
The most important circuit in the phase array is the phase shifter, which can be used to adjust the phase difference of each element signal, and then modulate the beam direction of the antenna array. However, it can be known from the theory of antenna arrays that if the amplitude of each element signal can be adjusted to make the antenna array non-uniformly excited, it can be used to adjust the side-lobe level of the beam. In chapter 5, we use TSMC 90-nm CMOS process to design a 35-GHz digitally controlled variable gain amplifier. The core part of the circuit is composed of five fully differential cascode stages in parallel. Input and output transformer are used for matching. The measurement results show that the S-parameters have a tendency toward low frequency deviation. The input return loss in fully open state shifts from 34.7 GHz to 29.6 GHz, the output return in fully open state loss shifts from 34.9 GHz to 30.6 GHz, and the gain in fully open state reduces from 13.9 dB to 10.3 dB. The peak value also shifts from 34.4 GHz to 29.8 GHz; at 29.8 GHz, the input return loss in all states is greater than 9.1 dB, the output return loss in all states is greater than 5.7 dB, and the gain in all states is up to 10.3 dB. The gain of 8 states is less than 0 dB, so the adjustable range of gain is 10.3 dB. The maximum phase shift in all states increases from 4.5± to 20±.
Because the output return loss of the measurement result is significantly worse than the simulation result, we resimulate the output transformer. In the resimulation, we consider the transistor lines that are not considered in the circuit simulation, and speculate that the capacitance of the output transformer might be caused by process variations to reduce the thickness between the M8 layer and the M9 layer. We resimulate the Cp,D in the circuit, and reduce the thickness between the M8 layer and the M9 layer by 40% to make the capacitance value better, thereby improving the output matching. Although reducing the thickness between the M8 layer and the M9 layer can make the S parameter′s frequency shift to the frequency of the measurement result, the gain can′t be reduced to the same as the measurement result. Then we speculate that the value of Q of the transformer in the simulation is too high, so we connecte a resistor of 1200 Ω in parallel next to the transformer to reduce the value of Q of the transformer. After we connect the resistors in parallel, the gain is reduced and can be close to the measurement result.
In this paper, we have successfully implemented a digital phase shifter and variable gain amplifier in the Ka band. Although the measurement results are quite different from the simulation results, after resimulating, we can know what effects the process will have in the Ka band. After considering these effects, the results can be closer to our expected performance. |
| 參考文獻 |
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