以CMOS/GaAs/GaN製程實現之應用於n79頻段J類寬頻功率放大器

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姓名

張瓊文(Chiung-Wen Chang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

以CMOS/GaAs/GaN製程實現之應用於n79頻段J類寬頻功率放大器
(Implementations on Class-J Wideband Power Amplifiers in CMOS/GaAs/GaN Technologies for n79 Band Applications)

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摘要(中)

本論文分別使用tsmc^TM 0.18 μm CMOS、穩懋WINTM 0.15-µm GaAs與0.25-µm GaN三種製程，設計同為操作於n79頻段之J類功率放大器。第二章會先探討n79頻段J類功率放大器，此架構會於之後章節，分別實現在三種不同製程之電路。
第三章提出應用tsmc^TM 0.18 μm CMOS製程於n79頻帶之J類功率放大器，電路設計採全積體化之兩層堆疊電晶體結構，量測結果為3-dB頻寬為3.0-5.8 GHz，在n79頻帶內，飽和效率皆大於35%，最大傳輸增益為14.06 dB，飽和輸出功率為20.13 dBm，1-dB 增益壓縮點輸出功率為17.06 dBm，晶片面積為1.2 (1.097 × 1.094) mm2。
第四章提出應用WINTM 0.15-µm GaAs製程於n79頻帶之J類功率放大器，電路設計採全積體化之兩級共源極電路架構，量測結果為3-dB頻寬為3.8 – 5.7GHz，在n79頻帶內，飽和效率皆大於35%，最大傳輸增益為25.42 dB，飽和輸出功率為23.43 dBm，1-dB 增益壓縮點輸出功率為22.34 dBm，晶片面積為1.5 (1.5 × 1.0) mm2。
第五章提出應用WINTM 0.25-µm GaN製程於n79頻帶之J類功率放大器，電路設計採全積體化之兩級共源極電路架構，量測結果為3-dB頻寬為3.1 – 5.3 GHz，在n79頻帶內，飽和效率皆大於40%，最大傳輸增益為24.56 dB，飽和輸出功率為38.33 dBm，1-dB 增益壓縮點輸出功率為25.16 dBm，晶片有效面積為3.57 (2.223 × 1.606) mm2。第六章為結論，並且比較三種製程各別之優缺點。

摘要(英)

The thesis developed three Class J power amplifiers that were designed in tsmc^TM 0.18-µm CMOS, WINTM 0.15-µm GaAs, and WINTM 0.25-μm GaN all for n79-band operations. The second chapter will firstly discuss the n79 band class J power amplifier. This implemented topology in three different process will be addressed in the following chapters.
The third chapter proposes a class J power amplifier using tsmc^TM 0.18-μm CMOS process in n79 frequency band. The circuit design adopted a fully integrated two-stacked FET structure. The amplifier achieves a 3-dB bandwidth from 3.0 to 5.8 GHz with small signal gain of 14.06 dB, the peak power added efficiency (PAE) is higher than 35% in n79 band. Continuous Wave (CW) measurements demonstrate a maximum saturated output power of 20.13 dBm and an OP1dB of 17.06 dBm, respectively. The chip size is 1.2 (1.097 × 1.094) mm2.
The fourth chapter proposes a class J power amplifier using WINTM 0.15-µm GaAs process in n79 frequency band. The circuit design adopted a fully integrated two-stage common-source circuit structure. The amplifier achieves a 3-dB bandwidth from 3.8 to 5.7 GHz with small signal gain of 25.42 dB, the peak PAE is higher than 35% in n79 band. CW measurements demonstrate a maximum saturated output power of 23.43 dBm and an OP1dB of 22.34 dBm, respectively. The chip size is 1.5 (1.5 × 1.0) mm2.
The fifth chapter proposes a class J power amplifier using WINTM 0.25-μm GaN process in n79 frequency band. The circuit design adopts a fully integrated two-stage common-source circuit structure. The amplifier achieves a 3-dB bandwidth from 3.1 to 5.3 GHz with a small signal gain of 24.56 dB, the peak PAE is higher than 40% in n79 band. CW measurements demonstrate a maximum saturated output power of 38.33 dBm and an OP1dB of 25.16 dBm, respectively. The chip effective area is 3.57 (2.223 × 1.606) mm2. The fifth chapter proposes conclusions of the thesis. The advantages and disadvantages of these processes will be analyzed and discussed in the thesis.

關鍵字(中)

★ n79頻段
★ 互補式金屬氧化物半導體
★ 砷化鎵
★ 氮化鎵
★ J類功率放大器
★ 疊接式功率放大器
★ 射頻發射機
★ 記憶效應
★ 鄰近通道功率
★ 誤差向量振福
★ 數位預失真
★ 小型基地站

關鍵字(英)

★ 5G small cell
★ ACPR
★ Class-J power amplifier
★ stacked FET
★ n79 band
★ RF transmitter
★ GaN
★ GaAs
★ CMOS
★ EVM
★ memory effect
★ digital pre-distortion

論文目次

摘要 VI
Abstract VII
誌謝 IX
目錄 X
圖目錄 XII
表目錄 XV
第一章緒論 1
1-1 研究動機 1
1-2 研究成果 2
1-3 章節簡介 2
第二章應用於n79頻段J類寬頻功率放大器 3
2-1 研究現況 3
2-2 J類功率放大器分析 6
2-3 考慮Cds非線性效應 9
第三章應用於n79頻帶之CMOS製程J類功率放大器 10
3-1 研究現況 10
3-2 疊接式功率放大器分析 11
3-3 應用於n79頻帶之CMOS製程J類功率放大器 14
3-3-1 應用於n79頻帶之CMOS製程J類功率放大器設計 14
3-3-2 電路模擬與量測結果 20
3-3-3 結果比較與討論 31
第四章應用於n79頻帶之砷化鎵製程J類功率放大器 34
4-1 研究現況 34
4-2 應用於n79頻帶之砷化鎵製程J類功率放大器 35
4-2-1 應用於n79頻帶之砷化鎵製程J類功率放大器設計 35
4-2-2 電路模擬與量測結果 39
4-2-3 結果比較與討論 50
第五章應用於n79頻段之氮化鎵瓦特級J類功率放大器 52
5-1 研究現況 52
5-2 應用於n79頻段之氮化鎵瓦特級J類功率放大器 53
5-2-1 應用於n79頻段之氮化鎵瓦特級J類功率放大器設計 53
5-2-2 電路模擬與量測結果 60
5-2-3 結果比較與討論 69
第六章結論 72
6-1 結論 72
6-2 未來方向 74
參考文獻 75

參考文獻

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指導教授

邱煥凱(Hwann-Kaeo Chiou)

審核日期

2022-6-27

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