應用於數位儲存示波器之100MHz CMOS 寬頻放大器電路設計

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姓名

蔡孟仁(Meng-Jen Tsai) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於數位儲存示波器之100MHz CMOS 寬頻放大器電路設計
(100MHz CMOS Wideband Amplifier for DSO)

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摘要(中)

寬頻放大器是通訊系統及高頻測試儀器中不可或缺的一部份。寬頻放大器是用在一段所需要頻寬中能提供一個穩定的增益。
本篇論文說明數位儲存示波器(DSO)所需的前級寬頻放大器的設計與實作。由於製程技術的提升，示波器的頻寬取樣率和精確度有了很大的進步。對寬頻放大器而言，頻寬需要達到所需的需求，但電晶體的寄生電容卻是限制頻寬的主要因素。在電路中每個信號路徑都會有個RC時間常數，這個常數常常決定了放大器頻寬。因此要使得寬頻放大器頻寬增加要設法降低RC時間常數。在這個寬頻放大器設計中，將採用並聯-並聯回授(Shunt-Shunt Feedback)的方式降低信號路徑的阻抗。
VLSI是目前世界的潮流趨勢,因此寬頻放大器的設計將採用CMOS的數位電路製程技術。整個電路是用TSMC0.6 CMOS 數位製程，佈局後模擬顯示在5V下，功率消耗為200mW，頻寬可達150MHz 晶片面積約佔1000umx1000um。

摘要(英)

Wideband Amplifier is indispensable in some high-frequency testing instruments and communication systems. A wideband amplifier is required in a analog front end that provides a flat gain transfer within the bandwidth.
In this thesis, the CMOS wideband amplifier was introduced, and implemented. Due to the processing technology improved, the bandwidth and the sampling rate of DSOs have a large development. To wideband amplifiers, the parasitic capacitors of transistors limited the bandwidth. In the circuits, every signal path has a RC time constant. This constant usually determines the bandwidth. So the topic of the wideband amplifier is to find a way to lower these RC time constants. In this wideband amplifier, we use an architecture of shunt-shunt feedback to reduce the impedances of signal-path nodes.
A GAIN-VGA-BUFFER architecture is employed in the circuit design. Simulation results show the SNR is about 45dB for 100mVpp up to 100Mhz. The chip is implemented by TSMC0.6um 1P3M process. It consumes 200mW for overall circuits by 5V power supply.

關鍵字(中)

★ 寬頻

關鍵字(英)

★ wideband
★ amplifier
★ 100MHz

論文目次

1.Introduction
1.1 Motivations ………………………………………10
1.2 Digital Storage Oscilloscope Basis…………………10
1.3 Thesis Organization……………………………………12
2.Wideband circuit techniques ……………………………….13
2.1 Feedback Topologies...………………………………………14
2.2 Pole-Zero Cancellation………………………………………16
2.3 Impedance Mismatch Technique………………………………18
3.Circuit Design and Post Layout Simulations ……………22
3.1 Specifications …...…………………………………………22
3.2 Circuit Design
3.2.1Block Diagram …………………………………………………23
3.2.2CMOS Shunt-Shunt Feedback Amplifier ...…………………23
3.2.3Gain Control Amplifier ….…………………………… …26
3.2.4Output Buffer ………………………………………………….27
3.2.5Variable Gain Amplifier ……………………………………27
3.2.6Bias Circuit.……………………………………………………29
3.3 Post Layout Simulations……………………………………29
4.Chip Measured Results…………………………………………40
5.Conclusions…………………………………………………….45
Appendix …...……………………………………………………………..49
A.1 2V Low-power IF/Baseband Signal Processor for IS-95 based CDMA Communication System ………………………………………………49
A.2 Measurement of the proposed 2V Low-power IF/Baseband Signal Processor for IS-95 based CDMA Communication System…………….51
References

參考文獻

[1] P Gray and R. Meyer, Analysis and Design of Analog Integrated Circuits, John Wiley & Sons, 1993.
[2] R. Parish, “Oscilloscopes for power electronic circuit”, IEE Colloquium on Measurement Techniques for Power Electronics, pp. 1-6.
[3] G. Cauffet and J.P. Keradec, “Digital oscilloscope measurements in high frequency power electronics“, Instrumentation and Measurement Technology Conference,
1992.IMTC’92., 9th IEEE, pp.445-447.
[4] M. Krau, H. Schniek and E. Wittig, “Fully-integrated 5V CMOS system for a 20Msample/s sampling oscilloscope”, ISSCC96, pp. 384-386, 1996.
[5] N. Kusayanagi, T. Choi, M.Hiwatashi, M. Segami, Y.Akasaka, and T. Wakabayashi, “A 25Ms/s 8-b 10Ms/s 10-b CMOS data acquisition IC for digital storage oscilloscopes”, IEEE J. of Solid-state circuit, vol.33, no. 3,pp. 492-496,1998.
[6] B. Gilbert, “A new wide-band amplifier technique”, IEEE J. of Solid-State Circuit, vol
[7] Chorng-Kuang Wang, Po-Chium huang and Chen-Yi huang, “ A fully differential CMOS transconductance-transimpedance wideband amplifier”, IEEE trans. Circuit syst. 11,vol. 42,no.11, pp.745-748,1995.
[8] J. Solomon and G. Wilson, “A Highly Desensitized Wide-Band Monolithic Amplifier”, IEEE Journal of Solid-State Circuits, Vol. 9, pp.167-175
[9] R. Meyer, R. Eschenbach, and R. Chin, “A wide-Band Untralinear Amplifier from 3 to 300MHz”, IEEE Journal of Solid-State Circuits, vol. 9 pp.167-175, Aug. 1974
[10] Z. Chang, and W. Sansen, Low Noise Wide-Band Amplifier in Bipolar and CMOS 0Techniques, kluwer Academic Publishers, 1991.
[11] A. Grebene, Bipolar and CMOS Analog Integrated Circuit Design, John Wiley & Sons, 1991.
[12] K.-Y. Toh, E. Meyer, D. Soo G.Chin, and A. Voschenkov, “Wide-Band, Low-Noise, Matched-Impedance Amplifier in Submicrometer MOS Technology”, IEEE Journal of Solid-State Circuits, vol. 22, pp.1031-1040, Dec. 1987.
[13] J. Mataya, G Haines, and S.Marshall, “IF Amplifier Using Cc Compensation Transistors”, IEEE Journal of Solid-State Circuits, vol. 3, pp. 401-407.
[14] T. Wakimono, and Y. Akazawa, “A Low-Power Wide-Band Amplifier Using a New Parasitic Capacitance Compensation Technique”, IEEE Journal of Solid-State Circuits, vol. 25, pp. 200-206, Feb. 1990.
[15] M. Ohara, Y. Akazawa, N. Ishihara, and S. Konaka, “Bipolar Monolithic Amplifier for a Gigabit Optical Repeater”, IEEE Journal of Solid-State circuits, vol. 19, pp.491-497, Aug. 1984
[16[ R. Apfet, and P. Gray, “A Fast-Setting Monolithic Operational Amplifier Using Doublet Compression Techniques”, IEEE Journal of Solid-State circuits, vol. 9, pp.332-340, Dec. 1974.
[17] E. Cherry and D. Hooper, “The Design of Wide-Band Transistor Feedback Amplifier”, Proc. of IEEE, vol. 110, pp.375-389, Feb 1963.
[18] H-M Rein and M. Moller, “Design Consideration for Very-High-Speed Si-Bipolar IC’s Operation up to 50Gb/s”, IEEE Journal of Solid-State circuits, vol. 31, pp. 1076-1090, Aug. 1996.
[19] C-K Wang, P.-C Huang and C.-Y Huang, “ A BiCMOS Limiting Amplifier for SONET OC-3”, IEEE Journal of Solid-State circuits, vol. 31, pp. 1197-1200, Aug. 1996.
[20] D. W. Faulkner, “ A Wideband Limiting Amplifier for Optical Fiber Repeater”, IEEE Journal of Solid-State circuits, vol. 18, pp. 333-340, Aug. 1983
[21] Hadidi, K.; Kobayashi, H. ”A 25MHz 20dB Variable Gain Amplifier” Instrumentation and Measurement Technology Conference, 1994. IMTC/94. Conference Proceedings. 10th Anniversary. Advanced Technologies in I & M., 1994 IEEE , 1994 , Page(s): 780 -783 vol.2
[22] P. J. G. van Lieshout and R.J. van de Plassche,” A power-efficient, low-distortion variable gain amplifier consisting of coupled differential pairs”, IEEE J. of Solid-State Circuits, vol.32, no.12, pp.21010-2110, 1997.
[23] R. Gomez and A. A. Abidi,” A 50-MHz CMOS variable gain amplifier for magnetic data storage”, IEEE J. of Solid-State Circuits, vol.27, no.6, pp.935-9393, 1992.
[24] J. Ramirez-Angulo, R. Sadkowski and E. Sanchez-Sinencio,” Linearity, accuracy and bandwidth considerations in wideband CMOS voltage amplifiers”, ISCAS ’93, vol.2, pp.1251-1254,1993.
[25] R.A. H. Balmford and W.Redman-White,” New high-compliance CMOS current mirror with low distortion for high-frequency circuits”, Electronics Letters, vol29, no.20, 1993.
[26] E About-ALLAM and E. I. E1-Masry,” Design of wideband CMOS current-mode operational amplifiers”, ISCAS’95 vol.3, pp.1556-1559, 1995.
[27] Kuang-Chan Liu and Chorng-Kuang Wang, “2V Low-power IF/Baseband Signal Processor for IS-95 based CDMA Communication System”, NCU thesis 97’.

指導教授

周世傑(Shyh-Jye Jou)

審核日期

2000-7-14

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