低雜訊輸出緩衝器設計及USB2實體層的傳收器製作

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：14

、訪客IP：3.138.141.202

姓名

郭淑華(Shu-Hua Kuo) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

低雜訊輸出緩衝器設計及USB2實體層的傳收器製作
(The Low Noise Output Buffer Design Techniques and Transceiver Implementation for USB2 Physical Layer)

相關論文

★ 低雜訊輸出緩衝器設計及USB2實體層的時脈回復器製作	★ 應用於通訊系統的內嵌式數位訊號處理器架構
★ 應用於數位儲存示波器之100MHz CMOS 寬頻放大器電路設計	★ 具有QAM/VSB模式的載波及時序回復之數位積體電路設計
★ 應用於通訊系統中數位信號處理器之模組設計	★ 應用於藍芽系統之CMOS射頻前端電路設計
★ 具有QAM/VSB 模式之多重組態可適應性等化器的設計與實現	★ 適用於高速通訊系統之可規劃多模式里德所羅門編解碼模組
★ 應用於橢圓曲線密碼系統之低複雜性有限場乘法器設計	★ 適用於通訊系統之內嵌式數位訊號處理器
★ 雷射二極體驅動電路	★ 適用於通訊系統的內嵌式數位信號模組設計
★ 適用在通訊應用之可參數化內嵌式數位信號處理器核心	★ 一個高速╱低複雜度旋轉方法的統一設計架構：角度量化的觀點
★ 5Gbps預先增強器之串列連結傳收機	★ 超取樣技術之資料回復電路設計及其模組產生器

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

高速I/O是決定電子裝置間能否成功傳送資料的重要因素。而同時性邏輯轉換雜訊(Simultaneous Switching Noise)又是高速數位電路中最主要的雜訊之一。所以在本論文中，首先我們先對同時性邏輯轉換雜訊做一概略性的介紹。接下來提出一個不但可以降低同時性邏輯轉換雜訊與電路輸出振盪問題而且還能維持驅動能力的AC/DC輸出緩衝器。並將以UMC 0.35um 1P5M的數位製程，來實際驗證理論分析及輸出級電路設計技巧。經由晶片量測的結果，我們在電路輸出震盪及同時性邏輯轉換雜訊上可以分別降低60%及40%。另外，我們也提出了一套特性化流程來估算SSO(Simultaneous Switching Outputs)所需的電源/接地對的個數及其所額外增加的延遲時間。
近來，萬用串列匯流排(Universal Serial Bus, USB)已經成為個人電腦平台中相當重要的一部份。USB能允許多種週邊裝置同時接上並且即插即用。因此在此篇論文中，我們設計了一個應用於此USB系統高速模式480Mb/s頻寬的傳收器，而此USB實體層系統中包含了一個傳收器(Transceiver)，兩個封包檢出器(Envelope Detector)及一個時脈回復器(Clock Recovery)。

摘要(英)

High-speed I/O is the key component to successfully transmit data between electronic devices. Simultaneous switching noise (SSN) or called ground bounce is one of the major noise sources in high-speed digital circuit. There are two research topics in this thesis. First we focus on the overview of SSN. We will propose an output buffer - AC/DC for reducing SSN, output signal ringing and maintain DC current capability. The test chip by using UMC 0.35um 1P5M digital process will be implemented to verify the theoretical analysis results and circuit design techniques. For example, SSO improvement from 3 to 11 for the YC2/ACDC2 cases, considering the Quiet VDD case. Measurement results show that our invention can reduce the output ringing by 60%, and VDD/GND line bounce by 40% when comparing with conventional buffers used in standard commercial cell library with 2ns rise/fall time and 40pF output loading capability. Also we propose a characterization procedure to estimate power pads for simultaneous switching outputs (SSO).
The Universal Serial Bus (USB) technology is now becoming an integral part of the personal computer platform. USB is one of the first I/O ports where several types of devices can be connected simultaneously. Thus, in the second research topic, the transceiver architecture and circuit is proposed for USB2 high-speed mode with 480Mb/s bandwidth. The physical layer of USB2 consists of transceiver, two envelope detector, and clock recovery.

關鍵字(中)

★ 同時性轉換雜訊
★ 接地反彈
★ 萬用串列匯流排
★ 同時性轉換輸出緩衝器

關鍵字(英)

★ SSN
★ Ground bounce
★ USB
★ SSO

論文目次

Contents
Abstract…………………………………………………………………i
Acknowledgements…………………………………………………ii
Contents………………………………………………………………iii
List of Figures………………………………………………………vii
List of Tables……………………………………………………………xi
1 Introduction……………………………………………………………………...1
1.1 Motivation………………………………………………………………….1
1.2 Thesis Organization……………………………………………………….3
2 Low Noise Output Buffer Design Techniques……………………………...4
2.1 Introduction……………………………………………………………..….4
2.2 The Analysis of Simultaneous Switching Noise and Simultaneous Switching Outputs…5
2.3 Summary of SSN reduction guideline…………………………………10
2.4 Overview of Simultaneous Switching Noise Reduction Techniques..11
2.4.1 Weighted and Distributed Method……………………………11
2.4.2 Low Bouncing Output Driver Method………………………12
2.4.3 CMOS Output Buffer with Reduced L-di/dt Noise…………13
2.4.4 Ground Bounce Isolated Output Buffer………………………15
2.5 Proposed Low Noise Output Buffer Design Techniques……………16
2.5.1 Design Techniques to reduce SSN and Output Ringing……17
2.5.2 Basic Operation…………………………………………………18
2.5.3 Simulation Results………………………………………………22
2.6 Summary…………………………………………………………………32
3 Characterization of Simultaneous Switching Outputs…………………33
3.1 Introduction……………………………………………………………....33
3.1.1 SSO Classification and Definition……………………………33
3.1.2 Static and Dynamic SSN Margin………………………………35
3.1.3 Simulation model for SSO………………………………………36
3.2 Characterization of Simultaneous Switching Outputs………………38
3.2.1 The Procedure of SSOP/SSOG Estimation……………………38
3.2.2 A Design Example of SSOG Characterization…………………40
3.3 Characterization of TSSO (Excess Incremental Delay) ………………42
3.3.1 The Procedure of TSSO Estimation………………………………43
3.3.2 A Design Example of TSSO Characterization…………………43
4 Test Chip Implementation and Measurement Results…………………46
4.1 Test Key for AC/DC Output Buffer…………………………………46
4.1.1 Testing Consideration…………………………………………47
4.1.2 Layout Implementation…………………………………………48
4.2 Measurement Results……………………………………………………51
4.3 Chip Summary……………………………………………………………63
5 Overview of USB2 Specifications…………………………………………65
5.1 Introduction………………………………………………………………65
5.2 Architecture Overview of USB2…......................................................66
5.2.1 USB2 System Description……..................................................66
5.2.2 USB2 Physical Interface…….........................................................67
5.2.3 USB2 Data Flow Type....................................................................68
5.2.4 USB2 Bus Protocol..........................................................................68
5.3 Overview of USB2 Transceiver.................................................................69
5.4 Specification of USB2 clock recovery.......................................................69
5.5 Summary......................................................................................................71
6 USB2 Transceiver Implementation………………………………………72
6.1 Introduction………………………………………………………………72
6.2 The Architecture of Transceiver for USB2……………………………75
6.3 The Circuit Design of Transmitter………………………………………76
6.3.1 Parallel Input Serial Output Circuit……………………………77
6.3.2 Driver and Current Source………………………………………79
6.3.3 Voltage Reference Circuit………………………………………80
6.3.4 Disconnection Envelop Detector………………………………81
6.4 The Circuit Design of Receiver………………………………………….83
6.4.1 Level Shifter and Differential to Single Circuit………………85
6.4.2 Transmission Envelop Detector…………………………………86
6.5 Summary…………………………………………………………………88
7 Conclusions……………………………………………………………………93
Bibliography………………………………………………………………………94

參考文獻

Bibliography
[1] R. Goyal, "Managing Signal Integrity," IEEE Spectrum, pp.54-58, Mar. 1994.
[2] W. C. Cheng, "Simultaneous Switching Noise Analysis and Synthesizer for Low Bouncing Output Driver," M.S. dissertation, Dep. Elec. Eng., National Central University, Taiwan, Jun. 1998.
[3] Y. T. Lin, "Investigation of Simultaneous Switching Noise for Signal Integrity in High Speed Digital Circuit Design," M.S. dissertation, Dep. Elec. Eng., National Central University, Taiwan, Jun. 1997.
[4] H. C. Chow, "CMOS Output Buffer With Reduced Ldi/dt Noise," US Patent no. 5,708,386, Jan. 1998.
[5] B. A. Sharpe-Geisler, S. Jose and Calif, "Groung Bounce Isolated Output Buffer," US Patent no. 5,438,277, Aug. 1995.
[6] 0.35um Cell Library of Faraday Technology Corp. - YC24, 1998.
[7] R. Senthinathan, J. L. Prince and S. Nimmagadda, "Effects of Skewing CMOS Output Driver Switching on the Simultaneous Switching Noise," 11th IEEE/CHMT International Electronics Manu. Tech. Symposium, pp.342-345, Sept. 1991.
[8] LCB600K Cell-Based ASIC Products Design Manual, LSI Logic Corp., Nov. 1996.
[9] "Simultaneous Switching Analysis Overview," ASIC Products Application Note of IBM, Aug. 1998.
[10] Universal Serial Bus specification revision 2.0, Mar. 2000.
[11] M. Horowitz, Chih-Kong Ken Yang and S. Sidiropoulos, "High-Speed Electrical Signaling: Overview and Limitations," IEEE Micro, vol.18, No.1, pp.12-24, Jan.-Feb. 1998.
[12] USB Implementers Forum web page at http://www.usb.org.
[13] Turi Aytur, Joe Gebits and Jason Golbus, "The Design of a High Speed Serial Link for IRAM," Berkeley University, cs254 Project Report, 12/8/1997. (http://iram.cs.berkeley.edu/serialio/cs254/)
[14] R. D. Chiao, "The Low Noise Output Buffer Design Techniques and Clock Recovery Implementation for USB2 Physical Layer," M.S. dissertation, Dep. Elec. Eng., National Central University, Taiwan, May 1999.
[15] S. J. Jou, W. C. Cheng and Y. T. Lin, "Simultaneous Switching Noise Analysis and Low Bouncing Buffer Design," IEEE Custom Integrated Circuits Conference, May 1998, pp.25.5.1-25.5.4.
[16] Senthinathan, G. Tubbs and M. Schuelein, "Negative Feedback Influence on Simultaneous Switching CMOS Outputs," IEEE 1988 Custom Integrated Circuits Conference, pp.5.4.1-5.4.5, May 1998.
[17] R. Vemuru, "Simultaneous Switching Noise Estimation for ASICs," IEEE International ASIC Conference and Exhibit 1995.
[18] A. Vaidyanath, B. Thoroddsen and J. L. Prince, "Effects of CMOS Driver Loading Conditions on Simultaneous Switching Noise," IEEE Trans. Comp., Packaging, Manu., Technol.-Part B, vol.17, No.4, pp.480-485, Nov.1994.
[19] R. Senthinathan and J. L. Prince, "Simultaneous Switching Ground Noise Calculation for Packaged CMOS Device," IEEE J. Solid-State Circuits, vol.26, No.11, pp.1724-1728, Nov. 1991.
[20] Sakurai and A. R. Newton, "Alpha-Power Law NOSFET Model and its Applications to CMOS Inverter Delay and other Formulas," IEEE J. Solid-State Circuits, vol.25, No.2, pp.584-594, Apr. 1990.
[21] R. Senthinathan and J. L. Prince, "Application Specific CMOS Output Driver Circuit Design Techniques to Reduce Simultaneous Switching Noise," IEEE J. Solid-State Circuits, vol.28, No.12, pp.1383-1388, Dec. 1993.

指導教授

周世傑(Shyh-Jye Jou)

審核日期

2000-6-12

推文