高速連結之時序與資料回復

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姓名

黃慕真(Mu-Jen Huang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

高速連結之時序與資料回復
(High Speed Link Timing and Data Recovery)

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摘要(中)

在本篇論文中，我們提出了一種新的時序與資料回復的方法。相較於傳統所用的鎖相迴路，我們採用了現今相當流行的相位選擇架構。在此設計中，我們利用對資料的五倍過取樣程序，從所獲得的訊息中萃取出資料轉變狀態的位置。由此，我們便可以知道最佳的資料取樣位置。
資料轉態的位置會受到靜態相位錯誤或相位抖動的影響而漂移，這樣的非理想現象將造成系統訊雜比與時序邊限的降低。因此，我們必須設法去追蹤這樣的漂移並且做資料回復。
在我們的設計中，利用了多數閘來增加資料的可信賴度，並且由互斥閘來得到資料轉態的情形。接下來我們使用信賴計數器來統計資料轉態的結果，並且決定最佳取樣點的位置。
除此之外，我們建立了一套資料錯誤率的預測與分析方法。由這個分析的結果，設計者可以根據所需要的規格來選擇適當的系統參數並避免做過多的錯誤嘗試。
最後，我們使用了可程式閘陣列來做硬體的功能驗證，並且內建了一個錯誤計數模組來計算資料錯誤的比率。

摘要(英)

In this thesis, a novel timing and data recovery algorithm for high-speed serial link is proposed. Instead of using the traditional PLL, we use the phase picking architecture. In our design, a 5X oversampling using multi-phase clocks are used to obtain the data information. And our purpose is to find the data transition position and pick the optimum phase for data sampling according to such information.
The transition point may move due to static phase error or jitters (dynamic phase error due to noise). These non-ideal effects cause the reduction of SNR and timing margin. So, the system should detect the phase errors and output a recovery clock to track it.
First, a majority voter chain is applied to enhance the data reliability. Then the transition position of each bit can be detected by XOR. The transition information are accumulated in the confidence counter and the machine will decide that whether the sampling phase should change. By such recovery mechanism, the sampling phase is fixed at the central point of data. Finally, according to the phase selected, three sample values are processed by a majority voter to obtain the recovered data.
Besides, we also develop an analysis method for bit error rate prediction according to the different system parameters. By the analysis results, one can decide the system parameters depend on the design specifications instead of iterations.
Finally, we use Xilinx FPGA for function simulation of the recovery system. Moreover, a bit error measurement modules are built in to test the system performance.

關鍵字(中)

★ 時序與資料回復

關鍵字(英)

★ High Speed Link
★ Data Recovery

論文目次

Contents
1. Introduction………………………………………………………1
1.1 Motivations………………………………………………………………1
1.2 Timing and Data Recovery Schemes in High Speed links………1
1.2.1 Clock Recovery in Phase or Delay Lock Loop…………2
1.2.2 Data Recovery Scheme of Phase Picker…………………2
1.3 Thesis Organization……………………………………………………4
2. Methodology of High Speed Link………………………………………5
2.1 Methodology Overview…………………………………………………5
2.2 Hardware Architecture…………………………………………………6
2.2.1 Oversampler……………………………………………………7
2.2.2 Data Process…………………………………………………7
2.2.3 Transition Detect……………………………………………8
2.2.4 Transition Decision Processor……………………………9
2.2.5 State Register……………………………………………………………10
2.2.6 Confidence Counter………………………………………11
2.2.7 LR counter………………………………………………………………12
2.2.8 Optimum Phase/Data Selector……………………………13
3. Bit Error Rate Analysis and Software Simulation……………15
3.1 BER Analysis…………………………………………………………………15
3.1.1 Non-ideal Effects…………………………………………15
3.1.2 Bit Error Probability with AWGN………………………16
3.1.3 BER Analysis for Clocked Data Recovery17
3.2 BER Analysis by Matlab……………………………………………20
3.2.1 BER versus Transition Position…………………………20
3.2.2 BER versus Majority Voter………………………………20
3.2.3 BER under Different Confidence Counter……………21
3.2.4 BER Analysis of Random Data…………………………23
3.2.5 Parameter Conclusion………………………………………23
3.3 BER Simulation………………………………………………………………23
3.3.1 Channel Model………………………………………………23
3.3.2 The eye Diagram when AWGN induced……………………24
3.3.3 Simulation Results of C program………………………25
3.3.4 Specifications Concluded…………………………………26
4. FPGA Simulation…………………………………………………27
4.1 Simulation Instrument………………….………………………………………27
4.2 Simulation Block Diagram…………………... …………………27
4.3 Multi-Phase Generator…………………... …………………... 28
4.4 Initialize…………………... …………………... ……………28
4.5 PRBS…………………... …………………... …………………...29
4.6 Channel………………….……………………...………………….…29
4.7 Recovery System…………………...…………………...………30
4.8 Optimum Clock and Data Selector………………….………………31
4.9 Matched Data Generator…………………... …………………...32
4.9.1 The pattern Detector………………….. ……………32
4.9.2 Configurations of the Matched Data Generator………33
4.10 Error Counter….. …………………... …………………... …35
4.11 Hardware Simulation Results…………………... ……………35
4.11.1 Function Simulation Results…………………... …36
4.11.2 BER Measurement…………………... ………………….37
4.11.3 Phasse Jitter of the Recovery Clock………………37
4.11.4 Frequency Error Endurance…………………... ………38
5. Conclusion………………………………………………………….40
6. Reference…………………………………………………………...41

參考文獻

[1] John Poulton and William J. Dally,” A tracking clock recovery receiver for 4Gb/s signaling,” IEEE Micro, p.25-p.27, Jan-Feb, 1998.
[2] Alen Fiedler etal, “ A 1.0625Gbps transceiver with 2X presampling and transmit pre-emphasis, “ ISSCC Conference, Session 15, p.238-p.239, Feb 1997.
[3] Ramin Farjad-Rad, Chih-Kong Ken Yang, Mark Horowitz and Thomas Lee, “ A 0.3um CMOS 8-Gb/s 4-PAM Serial Link Transceiver,”1999 Symposia on Technology and Circuits, Session 5, High Speed Link II.
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指導教授

蘇朝琴(Chauchin Su)

審核日期

2000-6-30

推文