1/8球面網格的構建及半導體元件的模擬

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姓名

楊子右(Yang-Zi-You) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

1/8球面網格的構建及半導體元件的模擬
(Construction of 1/8 Spherical Grid and Simulation of Semiconductor Devices)

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摘要(中)

本論文在C語言上開發出了一套三維半導體元件模擬架構，我們使用了帕松方程式(Poisson’s equation)、電子連續方程式(electron continuity equation)、電洞連續方程式(hole continuity equation)去描述三維空間中載子與電場的相互作用，並以這三個方程式為主軸去建立等效電路模型，最後再結合牛頓拉弗法(Newton Raphson method)以數值解的方式去求出方程式中的未知數，進而實現本論文中的模擬架構。我們會運用此模擬架構對不同結構的元件進行模擬量測，將理論值與手算估計值進行比較來佐證此模擬架構的準確度，為了確定此模擬架構在較複雜的3D結構中也能正確運作，本文選用了八分之一球、球殼進行模擬量測，我們會對八分之一球、球殼網格的建立步驟進行詳細的介紹，當中包括了如何避免網格封閉高斯面破裂，以及面臨量測節電不足時我們如何透過分割四面體去增加量測點使量測出的V-X圖能夠更為精準。

摘要(英)

In this thesis, we develop a set of three-dimensional semiconductor device simulation program structure based on C language. We use Poisson’s equation, electron continuity equation and hole continuity equation to describe the interaction between the carrier and the electric field in the three dimensional space. Based on these equations we can establish three equivalent circuit model respect to the three equations. And then we use Newton Raphson method to solve the unknows in the equations. Finally, combining these concept we can realize our three dimensional simulation program structure. We will use this simulation program structure to simulate different semiconductor components, and compare and discuss the theoretical and simulated characteristic curves to prove the accuracy of the device simulation program structure. In order to confirm that this device simulation program structure can work correctly in more complex 3D structures, this paper selects one-eighth sphere and spherical shell for simulation measurement. We will describe the detailed step of how to construct the model of one-eighth sphere and spherical shell, including how to avoid the grid closed Gaussian surface rupture, and how we can divide the tetrahedron to increase the measurement points to make the measured V-X diagram more accurate when faced with insufficient measurement nodes.

關鍵字(中)

★ 元件模擬
★ 1/8球面網格

關鍵字(英)

★ Simulation of Semiconductor Devices
★ 1/8 Spherical Grid

論文目次

摘要 i
Abstract ii
目錄 iii
圖目錄 iv
表目錄 vi
第一章簡介 1
第二章模擬架構推導 3
2.1元件網格的建立 4
2.2等效電路模型的建立 5
2.3牛頓-拉福森法建立A∆V=B矩陣 7
2.4六面體元件模擬 10
第三章八分之一球型網格建構及模擬 14
3.1八分之一球狀網格的建構 14
3.2八分之一球狀網格近似精確度 16
3.3八分之一球狀網格電阻值驗證 20
第四章八分之一球殼元件模擬 25
4.1八分之一球殼狀網格建立 25
4.2八分之一球殼高斯面討論 28
4.3網格精確性 29
4.4八分之一球殼PN接面 32
第五章結論 38
參考文獻 39

參考文獻

[1] James M. Fiore, Semiconductor Devices:Theory and Application. James M. Fiore via dissidents, April 2021.
[2] Brian W, Kernighan,Dennis M. Ritchie.C Programming Language (ANSI C) - 2nd edition.Prentice Hall,Inc,1988.
[3] Y. M. Li, “Research on Development of Computer Simulation Methods for Semiconductor Devices and Nanostructures,” D. S. Thesis, Institute of Electronics, National Chiao Tung University, Taiwan, Republic of China, 2000.
[4] R. A. Jabr, M. Hamad and Y. M. Mohanna, “Newton-Raphson Solution of Poisson’s Equation in a PN Diode”, International Journal of Electrical Engineering Education, 44.1, pp.23 - 33, Jan. 2007.
[5] W. G. Feng,” Newton-Raphson method of elastic viscoelastic finite element analysis”, M.S. Thesis,Institute of ME, National Chiao Tung University,
Taiwan,Republic of China,1984.
[6] A. R. Klivans, R. O′ Donnell and R. A. Servedio, “Learning Geometric Concepts via Gaussian Surface Area” 2008 49th Annual IEEE Symposium on Foundations of Computer Science, pp.541 - 550, Philadelphia, USA, Oct. 2008.
[7] K. C. Chien, “Finding Internal Vector from the Barycenter of Vector in Tetrahedron for 3-D Semiconductor Device Simulation”, Nation Central University, M. S. Thesis, Jun. 2017.
[8] K. C. Chien, “Finding Internal Vector from the Barycenter of Vector in Tetrahedron for 3-D Semiconductor Device Simulation”, Nation Central University, M. S. Thesis, Jun. 2017.
[9] Y. T. Liao, ” 3D Bridged Cube Element and Matrix Coefficient Verification and
Its Applications to Semiconductor Device Simulation”, M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2021.
[10] James Stewart, Daniel K. Clegg, Saleem Watson. Calculus: Early Transcendentals / Edition 9, Cengage Learning ,2020.
[11] J. H. Seo, Y. J. Yoon, S. Lee, J. H. Lee, S. Cho, and I. M. Kang, “Design and Analysis of Si-Based Arch-Shaped Gate-All-Around (GAA) Tunneling Field-Effect Transistor (TFET),” Current Applied Physics, vol. 15, pp.208-212, 2015.
[12] L. T, Wang, “Development of point-added cube element and its application to Semiconductor Device Simulation”, M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2018.
[13] Y. P. Chen ” 3D grounded cube element and matrix coefficient verification and its applications to semiconductor device simulation”, M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2021.

指導教授

蔡曜聰(Yao-Tsung Tsai)

審核日期

2022-7-5

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