3D快閃記憶體晶片測試和分析

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姓名

蔣昀劭(Yun-Shao Jiang) 查詢紙本館藏

畢業系所

資訊工程學系

論文名稱

3D快閃記憶體晶片測試和分析
(3D NAND Flash Testing and Analysis)

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至系統瀏覽論文 (2027-7-13以後開放)

摘要(中)

快閃記憶體已經被廣泛地用於計算機系統
儲存設備雖然快閃記憶體廣泛採用錯
誤校驗碼和讀取重試兩個方式來提升可靠性，但是在有些寫入資料的方式產生資料不
穩定的情況，也就是當資料寫入快閃記憶體但是讀取的時候卻容易發生錯誤位元過多
的情形，甚至因而產生致命錯誤，實驗中我們使用了兩個不同的快閃記憶體，透過實
驗找到如何寫入資料來降低錯誤位元的數量來減少致命錯誤的發生情況，測試在什麼
樣的寫入下資料會相對處於不穩定的狀態發現如果位於相同 WL的 Lower Page和
Upper Page皆有寫入資料並且沒有關閉下一條 WL將使資料不穩定而引發致命錯誤
進一步測試是否經過了 3,000次的寫入和讀取後，特性是否依然存在或是產生其他的影
響。

摘要(英)

Flash memory has been widely used in computer system storage devices. Although flash memory widely uses two methods of error check code and read retry to improve reliability, in some ways of writing data, data is not in a stable situation, that is, when data is written to the flash memory but read, it is prone to excessive error bits, and even fatal errors. In the experiment, we used two different flash memories. Experiment to find out how to write data to reduce the number of error bits to reduce the occurrence of fatal errors, test under what kind of writing data will be in a relatively unstable state, and find that if the Lower Page and Upper Page located in the same WL are both Having written data and not closing the next WL will make the data unstable and cause a fatal error. Further test whether the feature still exists or has other effects after 3,000 writes and reads.

關鍵字(中)

★ 快閃記憶體
★ 固態硬碟
★ 錯誤型式

關鍵字(英)

★ Flash Memory
★ SSD
★ Error Pattern

論文目次

摘要I
Abstract II
誌謝 III
目錄 IV
圖目錄 VI
表目錄 VIII
第一章、緒論 1
1.1 研究背景 1
1.2 研究目標 3
1.3 論文架構 3
第二章、技術回顧 4
2.1 快閃記憶體特性 4
2.1.1 NAND 記憶單元 6
2.1.2 如何讀取一個記憶單元 7
2.1.3 如何寫入一個記憶單元 8
2.1.4 如何抹除一個記憶單元 8
2.1.5 記憶單元壽命 9
2.1.6 資料打亂 - Data Scrambling 10
2.2 快閃記憶體控制原理 10
2.2.1 指令輸入週期 (Command Input Cycle) 12
2.2.2 位址輸入週期 (Address Input Cycle) 13
2.2.3 擦除操作 14
2.2.4 寫入操作 17
2.2.5 讀取操作 19
2.2.6 狀態讀取 21
2.2.7 讀取重試 23
2.3 MIAT系統設計方法論 25
2.3.1 IDEF0階層式的模組化設計 26
2.3.2 Grafcet離散事件建模 27
第三章、快閃記憶體測試 29
3.1 快閃記憶體測試流程模組化設計 29
3.1.1 基礎功能 30
3.1.2 讀取重試 30
3.1.3 P/E 31
3.2 快閃記憶體測試GRAFCET 32
3.2.1 基礎功能 32
3.2.2 讀取重試 33
3.2.3 P/E 34
第四章、實驗結果 36
4.1 實驗環境 36
4.2 基礎功能實驗 37
4.2.1 擦除操作 37
4.2.2 寫入操作 39
4.2.3 讀取操作 40
4.2.4 狀態讀取 41
4.3 讀取重試 41
4.3.1 1Z 2bpc 64Gb 2-Plane NAND Flash 42
4.3.2 3D NAND Flash Gen4 X3 256GB 2-Plane 45
4.4 P/E 47
4.4.1 P/E執行之前 47
4.4.2 P/E執行之後 49
第五章、結論 51
5.1 結論 51
5.2 未來展望 51
參考文獻 52
附錄一 54

參考文獻

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指導教授

陳慶瀚

審核日期

2022-8-3

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