| 摘要(英) |
In this paper, we generate random wafers by poisson yield model, generate synthetic wafers with different yields and different Diesize, and define the similarity formula. and the correlation between the similarity values.
Second discuss the analysis of similarity threshold. Under the same Diesize, we compare the data generated by the similarity formula on the synthetic wafers generated by poisson yield model with the data generated by the similarity formula on the real wafers, and the selected experimental object is the WM-811K provided by TSMC. Wafer database, define the correlation analysis between the similarity formula determination and the similarity threshold value of the wafer images in the same batch and their wafer Diesize.
Finally, the analysis and application of the similarity threshold on the real wafer map is discussed. The object of the experiment is the error state analysis in the real wafer. The real wafer we use is the WM-811K wafer database provided by TSMC. Divide it into several groups through the similarity threshold, find out the characteristics and connections of each group, and the error patterns can be divided into the following nine categories, Center, Donut, Scratch, Edge-Ring, Edge-Loc, Loc, Near- Full, Random, None.
Through the analysis method of the similarity threshold, the similarity formula is used to judge the wrong state association between the synthetic wafer and the real wafer, and the data of the synthetic wafer is adjusted and applied to the real wafer, so as to understand its characteristics, and finally can Determine what features the product has. |
| 參考文獻 |
[1] Ming-Ju Wu, Jyh-Shing Roger Jang, and Jui-Long Chen, “Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-Scale Data Sets”, IEEE Transactions on Semiconductor Manufacturing, Vol 28, pp. 1-12, Feb. 2015.
[2] Mill-Jer Wang, Yen-Shung Chang, J.E. Chen, Yung-Yuan Chen, and Shaw-Cherng Shyu, “Yield Improvement by Test Error Cancellation”, Asian Test Symposium (ATS′96), pp.258-260, Nov. 1996.
[3] Takeshi Nakazawa, and Deepak V. Kulkarni, “Wafer Map Defect Pattern Classification and Image Retrieval Using Convolutional Neural Network”, IEEE Transaction on Semiconductor Manufacturing, Vol 31, pp. 309-314, May. 2018.
[4] Jwu E Chen, Tung-Ying Lu, and Hsing-Chung Liang, “Testing the Spatial Pattern Randomness on Wafer Maps”, VLSI Test Technology Workshop (VTTW), Jul. 2019.
[5] Ya-Hsuan Wu, “Wafer Map Partition Analysis to Enhance Systematic Error Resolution”, M.S. thesis, Dept. Electron. Eng., National Central University, Taoyuan, Taiwan (R.O.C.), Apr. 2018.
[6] Cheng-Yan Wu, “Applications of Yield and Randomness Homogeneity Tests to Wafer Map Analysis”, M.S. thesis, Dept. Electron. Eng., National Central University, Taoyuan, Taiwan (R.O.C.), Jan. 2020.
[7] Tung-Ying Lu, “Application of Wafer Map Partition Analysis to Enhance the Salient Pattern Identification”, M.S. thesis, Dept. Electron. Eng., National Central University, Taoyuan, Taiwan (R.O.C.), Oct. 2019.
[8] Feng Zhou, Fernando De la Torre, Jessica K. Hodgins, “Hierarchical Aligned Cluster Analysis for Temporal Clustering of Human Motion”, IEEE Transactions on Pattern Analysis and Machine Intelligence, Vol 35, pp. 582-596, Mar. 2013.
[9] Ming-Ju Wu, Jyh-Shing R. Jang, Jui-Long Chen, “Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-Scale Data Sets”, IEEE Transactions on Semiconductor Manufacturing, Vol 28, pp. 1-12, Feb. 2015.
[10] Chia-Jui Wen, Jwu-E Chen, “Application of Similarity Cluster Analysis to the Real-world Wafer Lots”, National Central University, Taoyuan, Taiwan (R.O.C.), Oct. 2021. |
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