具可補償19-40 dB通道衰減之20 Gbps接收端自適應等化器

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姓名

黃清和(Ching-He Huang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具可補償19-40 dB通道衰減之20 Gbps接收端自適應等化器
(A 20 Gbps Adaptive RX Equalizer for 19-40 dB Channel Loss Compensation)

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至系統瀏覽論文 (2027-7-31以後開放)

摘要(中)

近年來，隨著近年半導體、消費性電子產品迅速發展，不論在短距離如晶片間或是長距離光纖通訊，資料傳遞頻寬皆日漸提升。然而，晶片與晶片間資料傳遞的通道頻寬並未隨之上升，使得資料經過傳輸通道的衰減越為嚴重，訊號品質因此下降，造成接收端進行資料判讀的難度大大提升，因此等化器在串列傳輸中扮演重要角色。
本論文提出一資料振幅相關自適應系統，讓等化器可以靈活運用到更寬廣的通道損失應用上，其利用資料振幅電壓位準來判斷資料是否為有效邏輯判斷，電路才會送給自適應系統進行補償調整，使自適應系統能夠正確收斂補償量，以避免資料在經過較高通道損失情況下，資料邏輯判斷錯誤造成自適應機制無法正確收斂的問題發生。而本論文在資料上則是整合連續時間線性等化器以及一階離散決策回授等化器來進行補償消除後游標資料符碼間干擾，以達到降低硬體複雜度與整體功率消耗的效果來補償資料。
本論文使用TSMC 40 nm (TN40G) 1P10M CMOS製程設計，電路操作電壓為0.9 V，輸入資料為20 Gb/s NRZ訊號，並利用PRBS7進行編碼，輸入時脈速率為10 GHz，於佈局後模擬等化器可補償之通道衰減範圍為19-40 dB，在通道衰減19 dB時，補償後之資料的峰對峰值抖動量為16.34 ps，方均根抖動量為4.30 ps;在通道衰減30 dB時，補償後之資料抖動峰對峰值為23.96 ps，方均根抖動量為4.90 ps；在通道衰減40 dB時，補償後之資料抖動峰對峰值為24.60 ps，方均根抖動量為5.34 ps。整體功率消耗為25.78 mW，其中CTLE以及DFE之等化器功率消耗為11.73 mW，自適應機制電路之功率消耗為14.05 mW，微縮後之晶片面積為0.998 mm2，其中核心電路面積為0.033 mm2。

摘要(英)

In recent years, as the rapid development of semiconductors, consumer electronics, artificial intelligence (AI), and internet of things (IoT), the required data rate has been increasing. However, the signal will be serious attenuated since the channel bandwidth is limited. It will make more difficultly to read data at the receiver end (RX). To meet the bandwidth requirement in high speed serial link, the equalizer should be preferentially considered to insert for data compensation. Furthermore, the adaptation would be added in order to allow the equalizer to be used flexibly in different frequency- and length-dependent cable losses application. The adaptive equalizer can adapt to best compensation and restore the signal integrity, so it plays an indispensable role in high speed serial link transmission system.
This thesis proposed a data-amplitude-dependent adaptive system which enables the equalizer to be flexibly applied in wider range of channel loss applications. In adaptive system, it will adjust compensation of equalizer when detecting data voltage level large enough. This method can avoid the problem that the adaptive system can’t converge correctly due to wrong data logic decision in high channel loss. Furthermore, only continuous time linear equalizer (CTLE) and 1-tap discrete-time decision feedback equalizer (1-tap DT-DFE) are be used in data compensation. As the result, the proposed adaptive equalizer system not only reduce the complexity of hardware and power consumption, but also can be widely used for 19-40 dB channel loss application.
This chip is fabricated by TSMC 40 nm (TN40G) 1P10M CMOS process. In simulation result, the input is 20 Gb/s PRBS7 NRZ data, and the 10 GHz half rate clock be adopted. In 19-dB channel loss, the simulated peak-to-peak jitter of equalized NRZ data is 16.34 ps, and the root mean square (RMS) jitter is 4.30 ps. In 30-dB channel loss, the simulated peak-to-peak jitter of equalized NRZ data is 23.96 ps, and the root mean square (RMS) jitter is 4.90 ps. In 40-dB channel loss, the simulated peak-to-peak jitter of equalized NRZ data is 24.60 ps, and the root mean square (RMS) jitter is 5.34 ps. The overall power consumption of whole adaptive equalizer system consumes 25.78 mW at 0.9 V supply voltage, which including power of equalizer 11.73 mW and power of adaptive system 14.05 mW. The chip area with 40 nm which is scaling down by 45 nm is 0.998 mm2 and core area is 0.033 mm2.

關鍵字(中)

★ 自適應等化器
★ 連續時間線性等化器
★ 決策回授等化器
★ 資料振幅相關逼零演算法
★ 標誌最小均方演算法
★ 高通道衰減應用

關鍵字(英)

★ Adaptive Equalizer
★ Continuous-Time Linear Equalizer (CTLE)
★ Decision Feedback Equalizer (DFE)
★ Data Amplitude Dependent Zero-Forcing Algorithm (DAD-ZF)
★ Sign-Sign Least Mean Square Algorithm (SSLMS)
★ High Channel Loss Application

論文目次

摘要 i
Abstract ii
誌謝 iv
目錄 vi
圖目錄 ix
表目錄 xv
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 4
第2章高速串列傳輸之訊號完整性 6
2.1 隨機二元資料 6
2.1.1 隨機二元資料特性 6
2.1.2 資料格式 8
2.1.3 資料編碼形式 8
2.1.4 傳輸線理論[8] 10
2.2 抖動分析 17
2.2.1 隨機抖動 18
2.2.2 定量性抖動 19
2.2.2.1 資料相關抖動 19
2.2.2.2 工作週期失真 20
2.2.2.3 週期性抖動 21
2.3 單一位元脈衝響應與等化器之關係 22
2.4 眼圖分析 24
2.5 誤碼率[5] 26
第3章等化器與自適應機制之背景介紹 30
3.1 等化器的種類 30
3.1.1 連續時間線性等化器(CTLE) 31
3.1.2 決策回授等化器(DFE) 33
3.1.3 前饋式等化器(FFE) 36
3.2 自適應機制 37
3.2.1 頻譜平衡技術 37
3.2.2 最小均方演算法(LMS) 39
3.2.2.1 SS-LMS之硬體實現 42
3.2.2.2 SS-LMS之使用限制 44
3.2.3 逼零演算法(Zero-Forcing Algorithm) 46
3.2.4 張眼顯示器 48
3.3 等化器電路文獻探討 50
3.3.1 多階數決策回授等化器(Multi-Tap DFE) 50
3.3.2 有限/無限脈衝響應決策回授等化器(FIR/IIR DFE) 51
3.3.3 類比轉數位形式之接收器(ADC-based Receiver) 52
3.4 比較與討論 53
第4章自適應等化器之架構設計與實現 55
4.1 設計流程 55
4.2 電路架構 56
4.3 操作說明 58
4.3.1 資料補償路徑 58
4.3.2 自適應系統 59
4.4 系統分析 61
4.4.1 決策回授等化器迴路分析 61
4.4.2 自適應系統迴路分析 63
4.5 行為模擬 69
4.6 子電路實現與分析 74
4.6.1 連續時間線性等化器(CTLE) 74
4.6.2 一階離散時間決策回授等化器(1-Tap DT-DFE) 76
4.6.3 自適應系統(Adaptive System) 79
4.6.3.1 資料振幅相關型樣偵測器 81
4.6.3.2 自適應演算系統(Adaptive Algorithm) 83
4.6.3.3 增益補償調整電路(Gain Adjustment Circuit) 86
4.6.3.4 迴路切換機制(Loop Switch Mechanism) 89
4.6.3.5 決策回授等化器啟動電路(DFE Startup Circuit) 90
4.7 模擬結果 92
4.7.1 通道模型 92
4.7.2 佈局前模擬(Pre-Layout Simulation) 95
4.7.2.1 短通道模擬(Channel Loss = 19 dB @ 10 GHz) 95
4.7.2.2 中長通道模擬(Channel Loss = 30 dB @ 10 GHz) 98
4.7.2.3 長通道模擬(Channel Loss = 40 dB @ 10 GHz) 101
4.7.3 佈局後模擬(Post-Layout Simulation) 104
4.7.3.1 短通道模擬(Channel Loss = 19 dB @ 10 GHz) 104
4.7.3.2 中長通道模擬(Channel Loss = 30 dB @ 10 GHz) 107
4.7.3.3 長通道模擬(Channel Loss = 40 dB @ 10 GHz) 110
4.7.4 模擬結果之統整與比較 113
4.7.4.1 佈局前模擬 113
4.7.4.2 佈局後模擬 116
第5章晶片佈局與量測 119
5.1 電路佈局 119
5.1.1 晶片封裝 120
5.1.2 佈局與電源配置 122
5.2 量測考量 123
5.2.1 量測環境 123
5.2.2 高頻輸入緩衝器 124
5.2.3 高頻輸出緩衝器 126
5.2.4 M8048A ISI通道 129
5.3 晶片與印刷電路版照相 130
5.4 量測結果 131
5.4.1 晶片輸出之眼圖 131
5.4.2 晶片問題與分析 133
5.5 規格比較表 136
第6章結論 139
6.1 結論 139
6.2 未來研究方向 140
附錄 142
參考文獻 145

參考文獻

[1] VESA DisplayPort Standard, Version 2.0, Jun. 2019.
[2] Universal Serial Bus 4 Specification, Version 1.0, May 2021.
[3] Serial ATA Specification, Revision 3.5a, SATA-IO, Mar. 2021.
[4] PCI Express Base Specification, Revision 6.0, Version 1.0, PCI-SIG, Jan. 2022.
[5] 孫世洋, “以符碼間干擾偵測技術實現自適應等化器之 5 Gbps 半速率時脈與資料回復電路,” 碩士論文, 國立中央大學, 2016.
[6] B. Razavi, “Basic concepts,” in Design of Integrated Circuits for Optical Communications, 1st ed. New York, NY, USA: McGraw-Hill, 2003, ch. 2, sec. 1, pp. 8-11.
[7] A. X. Widmer and P. A. Franaszek, “A DC-balanced, partitioned-block, 8B/10B transmission code,” IBM Journal of Research and Development, vol. 27, no. 5, pp. 440-451, Sept. 1983.
[8] F. T. Ulaby and U. Ravaioli, “Transmission Lines,” in Fundamentals of Applied Electromagnetics, 6th ed. United Kingdom: Pearson, 2015, ch. 2, pp. 62-134.
[9] Tektronix, “時序水平抖動的認識和特性分析”. Available: https://www.tek.com/tw/solutions/application/jitter-measurement-and-timing-analysis.
[10] B. Razavi, “Noise,” in Design of Analog CMOS Integrated Circuits, 2nd ed. New York, NY, USA: McGraw-Hill, 2017, ch. 7, pp. 201-239.
[11] R. Sarpeshkar, T. Delbruck and C. A. Mead, “White noise in MOS transistors and resistors,” IEEE Circuits and Devices Magazine, vol. 9, no. 6, pp. 23-29, Nov. 1993.
[12] Agilent Technologies, “Jitter Fundamentals: Agilent 81250 ParBERT Jitter Injection and Analysis Capabilities,” Application Note: 5988-9756EN, July 17, 2003.
[13] N. Na, D. M. Dreps and J. A. Hejase, “DC wander effect of DC blocking capacitors on PCIe Gen3 signal integrity,” in Proc. IEEE 63rd Electronic Components and Technology Conference, May 2013, pp. 2063-2068.
[14] Y. Wu, “An improved statistical analysis method for duty cycle distortion jitter analysis,” in Proc. IEEE International Symposium on Consumer Electronics (ISCE), Jun. 2013, pp. 31-32.
[15] N. Radhakrishnan, B. Achkir, J. Fan and J. L. Drewniak, “Stressed jitter analysis for physical link characterization,” in Proc. IEEE International Symposium on Electromagnetic Compatibility, Feb. 2010, pp. 568-572.
[16] Agilent Technologies, “Finding sources of jitter with real-time jitter analysis,” 2008.
[17] SHF Communication Technologies AG, “Application Note AN-JITTER-1-Jitter Analysis using SHF 10000 Series Bit Error Rate Testers,” 2005.
[18] K. Cheng, Y. Tsai, Y. Wu, and Y. Lin, “A 5-Gb/s inductorless CMOS adaptive equalizer for PCI express generation II applications,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 57, no. 5, pp. 324-328, May 2010.
[19] J. W. Jung and B. Razavi, “A 25 Gb/s 5.8 mW CMOS equalizer,” IEEE J. Solid-State Circuits, vol. 50, no. 2, pp. 515-526, Feb. 2015.
[20] A. Agrawal, J. Bulzacchelli, T. Dickson, Y. Liu, J. Tierno and D. Friedman, “A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 3220–3231, Dec. 2012.
[21] 許馥淳, “應用在序列傳輸系統之 10-Gbps 離散時間適應性等化器,” 碩士論文, 國立交通大學, 2009.
[22] K. -Y. Chen, W. -Y. Chen and S. -I. Liu, “A 0.31-pJ/bit 20-Gb/s DFE with 1 discrete tap and 2 IIR filters feedback in 40-nm-LP CMOS,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 64, no. 11, pp. 1282-1286, Nov. 2017.
[23] 陳紫宜, “具高通濾波補償之10 Gb/s全速率自適應四階脈波振幅調變等化器,” 碩士論文, 國立中央大學, 2019.
[24] J. Lee, “A 20-Gb/s adaptive equalizer in 0.13-µm CMOS technology,” IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 1999-2011, Sep. 2007.
[25] S. Haykin, “Wiener Filters,” in Adaptive Filter Theory, 5th ed., United Kingdom: Pearson, 2012, ch. 2, pp. 90-122.
[26] Y. Hidaka et al., “A 4-channel 1.25-10.3 Gb/s backplane transceiver macro with 35 dB equalizer and sign-based zero-forcing adaptive control,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3547-3559, Dec. 2009.
[27] H. Won et al., “A 28-Gb/s receiver with self-contained adaptive equalization and sampling point control using stochastic sigma-tracking eye-opening monitor,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 64, no. 3, pp. 664-674, March 2017.
[28] 陳俊諺, “以逼零演算法實現無外部校正之單一自適應系統之5 Gbps全速率連續時間線性等化器與決策回授等化器,” 碩士論文, 國立中央大學, 2018.
[29] J. Im et al., “A 40-to-56 Gb/s PAM-4 receiver with ten-tap direct decision-feedback equalization in 16-nm FinFET,” IEEE J. Solid-State Circuits, vol. 52, no. 12, pp. 3486-3502, Dec. 2017.
[30] K. -Y. Chen et al., “A 0.31-pJ/bit 20-Gb/s DFE with 1 discrete tap and 2 IIR filters feedback in 40-nm-LP CMOS,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 64, no. 11, pp. 1282-1286, Nov. 2017.
[31] S. Kiran et al., “A 52-Gb/s ADC-based PAM-4 receiver with Comparator-assisted 2-bit/stage SAR ADC and partially unrolled DFE in 65-nm CMOS,” IEEE J. Solid-State Circuits, vol. 54, no. 3, pp. 659-671, March 2019.
[32] Y. -H. Kim et al., “A 21-Gbit/s 1.63-pJ/bit adaptive CTLE and one-tap DFE with single loop spectrum balancing method,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 24, no. 2, pp. 789-793, Feb. 2016.
[33] S. Li, Y. Jiang and P. Liu, “An adaptive PAM-4 analog equalizer with boosting-state detection in the time domain,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 25, no. 10, pp. 2907-2916, Oct. 2017.
[34] Keysight, “M8048A ISI Channels - Data Sheet”.
[35] T. Kawamoto et al., “Multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-tap DFE and data-rate-adjustment PLL in 28nm CMOS,” ISSCC Dig. Tech. Papers, pp. 1-3, Feb. 2015.
[36] B. Zhang et al., “A 28 Gb/s multistandard serial link transceiver for backplane applications in 28 nm CMOS,” IEEE J. Solid-State Circuits, vol. 50, no. 12, pp. 3089-3100, Dec. 2015.
[37] Y. Frans et al., “A 56-Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16-nm FinFET,” IEEE J. Solid-State Circuits, vol. 52, no. 4, pp. 1101-1110, April 2017.
[38] T. Norimatsu et al., “A 100-Gbps 4-lane transceiver for 47-dB loss copper cable in 28-nm CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 67, no. 10, pp. 3433-3443, Oct. 2020.
[39] A. Roshan-Zamir et al., “A 56-Gb/s PAM4 receiver with low-overhead techniques for threshold and edge-based DFE FIR- and IIR-tap adaptation in 65-nm CMOS,” IEEE J. Solid-State Circuits, vol. 54, no. 3, pp. 672-684, March 2019.
[40] J. Lee et al., "A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s video interface receiver with jointly adaptive CTLE and DFE using biased data-level reference,” IEEE J. Solid-State Circuits, vol. 55, no. 8, pp. 2186-2195, Aug. 2020.
[41] 謝文軒, “具高通濾波補償之10 Gb/s全速率自適應四階脈波振幅調變等化器,” 碩士論文, 國立中央大學, 2020.

指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2022-8-11

推文