| 摘要(英) |
Synthetic Aperture Radar imaging can actively perform imaging without being affected by weather, and real-time imaging can greatly increase its application value and reduce the transmission volume of raw echo signals. However, real-time processing with large image sizes needs an efficient architecture for high-speed operations. In this thesis, range Doppler algorithm is implemented to complete the entire imaging operation. For range Doppler algorithm, the two-dimensional fast Fourier transform consumes more than 80% computation time. In order to meet the requirements of real-time imaging, it is important to arrange the data flow of the remaining modules to match with the data flow of the two-dimensional fast Fourier transform. In addition, the entire range Doppler algorithm includes four steps: range compression, secondary range compression, range cell migration correction and azimuth compression. This research focuses on the data transfer and processing among these steps, reducing hardware resources by scheduling as well as hardware sharing, and improving the operating frequency by using pipelines. With well-scheduled parameter calculation, the streaming input and output of SAR signals can be satisfied. This hardware supports three range FFT sizes, including 8192, 16384, and 32768, and the azimuth FFT size is fixed at 8192. The operation frequency is 100MHz. The datapaths contain three different precisions, double precision, customized floating-point and fixed-point representation to tradeoff performance and complexity. The Xilinx Evaluation board Virtex UltraScale+ HBM VCU128 FPGA is used. Multiple AXI ports are connected to offer the data transfer rate of about 50Gbps. Finally, the processing time of a 8K×32K image is 1.36s, and the echo signal acquiring time is 1.6s. The goal of real-time processing is achieved. |
| 參考文獻 |
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[3] 李鈺傑, "合成孔徑雷達成像及都普勒參數估測改良, " 碩士論文, 國立中央大學電機工程學系, 2020
[4] 莊博仁, "合成孔徑雷達成像演算法及都普勒參數估測之研究, " 碩士論文, 國立中央大學電機工程學系, 2019
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[6] Z. Ding et al., "A Modified Fixed-Point Chirp Scaling Algorithm Based on Updating Phase Factors Regionally for Spaceborne SAR Real-Time Imaging," in IEEE Transactions on Geoscience and Remote Sensing, vol. 56, no. 12, pp. 7436-7451, Dec. 2018, doi: 10.1109/TGRS.2018.2852062.
[7] H. Breit, S. Mandapati and U. Balss, "An FPGA/MPSoC Based Low Latency Onboard SAR Processor," 2021 IEEE International Geoscience and Remote Sensing Symposium IGARSS, 2021, pp. 5159-5162, doi: 10.1109/IGARSS47720.2021.9553539.
[8] L. Dong, X. Meng and D. Zhu, "High-Squint SAR Imaging Technique Based on Multi-Chip DSP," 2021 7th Asia-Pacific Conference on Synthetic Aperture Radar (APSAR), 2021, pp. 1-5, doi: 10.1109/APSAR52370.2021.9688347.
[9] W. Yu, Y. Xie, D. Lu, B. Li, H. Chen and L. Chen, "Algorithm Implementation of On-Board SAR Imaging on FPGA+DSP Platform," 2019 IEEE International Conference on Signal, Information and Data Processing (ICSIDP), 2019, pp. 1-5, doi: 10.1109/ICSIDP47821.2019.9173188. |
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