應用於Sub-6 GHz n79 頻段互補式金氧半導體 F23 類壓控振盪器與使用動態偏壓B/C類混合式壓控振盪器暨整數型鎖相迴路之研製

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：110

、訪客IP：18.226.251.74

姓名

賴柏儒(Po-Ju Lai) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於Sub-6 GHz n79 頻段互補式金氧半導體 F23 類壓控振盪器與使用動態偏壓B/C類混合式壓控振盪器暨整數型鎖相迴路之研製
(Implementations on CMOS Sub-6 GHz n79 band Class-F23 Voltage Control Oscillator, Dynamic Biasing Class-B/C Hybrid-Mode Voltage Controlled Oscillator, and Integer-N Phase Locked Loop)

相關論文

★ 應用於筆記型電腦數位電視單極天線之研製	★ 應用於數位機上盒與纜線數據機之電纜多媒體傳輸標準多工濾波器
★ 印刷共面波導饋入式多頻帶與超寬頻天線設計	★ 微波存取全球互通頻段前向匯入式功率放大器與高效率Class F類功率放大器暨壓控振盪器電路之研製
★ 應用於矽基功率放大器與混頻器之傳輸線型變壓器研究	★ 應用於V-頻段射頻收發機前端電路之低功耗源極注入式混頻器之研製
★ 應用積體電路上方後製程與整合被動元件於互補式金氧半導體製程之系統封裝研究	★ 應用fT-倍頻電路架構於毫米波壓控振盪器與注入鎖定除頻器之研製
★ 應用傳輸線型變壓器於X/K–Ka/V頻段全積體整合之寬頻互補式金氧半導體功率放大器研製	★ 應用於K / V 頻段低功耗混頻器之研製
★ 應用於K/V頻段之低功耗CMOS低雜訊放大器之研究	★ 應用於5-GHz CMOS射頻前端電路之低電壓自偏壓式混頻器與高線性化功率放大器之研製
★ 應用於 K 頻段射頻接收機之寬頻低功耗 CMOS 低雜訊放大器之研製	★ 應用磁耦合變壓器於K頻段之低功耗互補式金氧半導體壓控振盪器研製
★ 應用於K頻段之單向化全積體整合功率放大器與應用於V頻段之寬頻功率放大器研製	★ 應用於C/X頻段全積體整合之互補式金氧半導體寬頻低功耗降頻器與寬頻功率混頻器之研製

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

至系統瀏覽論文 ( 永不開放)

摘要(中)

本論文擬研究射頻收發機中之本地振盪源相關電路，研製應用於第五代行動通訊(5th generation wireless systems)之n79頻段本地振盪電路。本論文首先介紹相位雜訊與LC振盪器中用以分析相位雜訊的模型以及介紹何謂flicker noise upconversion，接著介紹尾濾波與二次諧波共振技術，最後介紹所實現之電路。本論文一共實現三種電路，皆使用tsmcTM 0.18 μm互補式金氧半導體製程製作，內容如下所述：
I.低相位雜訊n79頻段F23類壓控振盪器
本電路實作具有低相位雜訊特性之F23類壓控振盪器，使用變壓器耦合實作F23類共振腔，並獨立主、副線圈中心抽頭偏壓以優化直流功耗。整體電路經由量測後，可調頻率為4.39 ~ 5.04 GHz (13.8 %)，電路功耗為5.64 ~ 7.01 mW，相位雜訊在 1-MHz 偏移頻率下最低為−122.56 dBc/Hz，對應 FoM最高為−187.15 dBc/Hz，整體晶片面積包含I/O PAD為1.1 × 1 mm2。
II.使用動態偏壓低雜訊低功耗B/C類混合式壓控振盪器
本電路實作具有低功耗、低相位雜訊特性之B/C類混合式壓控振盪器，C類振盪器具有低功耗、高電流效率以及低相位雜訊之特性，並且提出使用動態偏壓以及操作在B類的PMOS輔助振盪，使振盪器可以穩定起振。整體電路經由量測後，可調頻率為4.42 ~ 5.07 GHz (13.63 %)，電路功耗為3.44 ~ 3.54 mW，相位雜訊在 1-MHz 偏移頻率下最低為−119.09 dBc/Hz，對應 FoM最高為−186.55 dBc/Hz，整體晶片面積包含I/O PAD為0.98 × 0.86 mm2。

III.利用B/C類混合壓控振盪器之n79頻段整數型鎖相迴路
本電路包含使用動態偏壓的B/C類混合式壓控振盪器、電流模式邏輯除頻器、雙轉單緩衝放大器、真單一相位時脈除頻器、全擺幅緩衝器、相位頻率比較器、電荷幫浦以及迴路濾波器，利用上述電路合成一個鎖相迴路，並於章節中完整分析各子電路之用途及數學分析。整體電路經由量測後，當輸入參考頻率為35 MHz到38.125 MHz時輸出頻率能成功鎖定在4.48 GHz到4.88 GHz，除數設計為128，整體鎖相迴路功耗為25.66 mW，在中心頻4.7 GHz時量測後參考突波大小為-47.26 dBc，鎖定後相位雜訊在1 MHz偏移時為-99.31 dBc/Hz，整體晶片面積包含I/O PAD為1.26 × 0.97 mm2。

摘要(英)

This thesis aims to design local oscillator (LO) circuits for the signal source of the fifth generation (5G) cellular communications in n79 band transceivers. In this thesis, we firstly introduce the phase noise and LC oscillator models used to analyze phase noise and what is flicker noise upconversion, then explain the tail filter and second harmonic resonance topology, and finally illustrate the circuit implemented in this thesis. In this thesis, three LO circuits were implemented in tsmcTM 0.18 μm CMOS processes. The developed LO circuits are listed as follow,
I.A low phase noise n79-band Class-F23 VCO
Class-F23 oscillator features the low phase noise. In this work, we use transformer coupling technique to realize Class-F23 LC-tank, and separate the center tape of the primary and secondary coils to optimize the DC power consumption. The measurements are listed as below, the operation frequency is from 4.39 to 5.04 GHz (i.e., 13.8% tuning range), and the power consumption is from 5.64 to 7.01 mW. The lowest phase noise at 1-MHz offset frequency is −122.56 dBc/Hz which is correspondent to the FoM of −187.15 dBc/Hz. The chip size included pads is 1.1× 1 mm2.
II.A dynamic biasing low phase noise and low power consumption on Class-B/C Hybrid-Mode VCO
The Class-C oscillator has the features of low power consumption, high current efficiency and low phase noise. In this work, we proposed a dynamic bias circuit and PMOS auxiliary oscillation operating in Class-B to solve hard start-up problem of the Class-C oscillator. The measurements are listed as below, the operation frequency is from 4.42 to 5.07 GHz (i.e., 13.63% tuning range), and the power consumption is from 3.44 to 3.54 mW. The lowest phase noise at 1-MHz offset frequency is −119.09 dBc/Hz which is correspondent to the FoM of −186.55 dBc/Hz. The chip size included pads is 0.98× 0.86 mm2.
III.An integer-N Phase Locked Loop (PLL) with Class-B/C Hybrid-Mode VCO
The functional circuit blocks of the designed PLL include a dynamic biasing Class-B/C Hybrid-Mode voltage controlled oscillator, a current mode logic divider, a differential to single buffer, a TSPC divider, a phase and frequency detector, a charge pump, and a loop filter. This thesis analyzes the behavior model of the PLL. The measurements are listed as, the PLL is locked from 4.48 to 4.88 GHz when reference signal is 35 to 38.125 MHz. The division ratio is 128 and the total power consumption is 25.66 mW. At the center frequency of 4.7 GHz, the reference spur is as low as -47.26 dBc and phase noise is -99.31 dBc/Hz at 1-MHz offset. The chip size included pads is 1.26 × 0.97 mm2.

關鍵字(中)

★ 互補式金屬氧化物半導體
★ B/C類
★ F類
★ 壓控振盪器
★ 鎖相迴路
★ 動態偏壓

關鍵字(英)

★ CMOS
★ Class-B/C
★ Class-F
★ Voltage-Controlled Oscillator (VCO)
★ Phase Locked Loop(PLL)
★ Dynamic Biasing

論文目次

摘要 I
Abstract III
誌謝 V
目錄 VI
圖目錄 VIII
表目錄 XI
第一章緒論 1
1-1 研究動機 1
1-2 研究成果 2
1-3 章節簡介 2
第二章低相位雜訊n79頻段F23類壓控振盪器 3
2-1 相位雜訊簡介 3
2-2 壓控振盪器簡介 6
2-3 尾濾波及二次諧波共振簡介 12
2-4 F23類壓控振盪器設計 14
2-5 量測與模擬結果 22
2-6 結果與討論 28
第三章使用動態偏壓低雜訊低功耗B/C類混合式壓控振盪器 30
3-1 C類壓控振盪器電流及振幅分析 30
3-2 B/C類混合式壓控振盪器設計 33
3-3 量測與模擬結果 40
3-4 結果與討論 47
第四章利用B/C類混合壓控振盪器之n79頻段整數型鎖相迴路 49
4-1 鎖相迴路基本架構簡介 49
A. 壓控振盪器 50
B. 除頻器 51
C. 相位頻率比較器 52
D. 電荷幫浦 53
E. 迴路濾波器 54
4-2 鎖相迴路迴路分析 56
4-3 鎖相迴路架構及各子電路分析 62
4-3-1 壓控振盪器 63
4-3-2 電流模式邏輯除頻器 69
4-3-3 雙轉單緩衝放大器 70
4-3-4 真單一相位時脈除頻器 71
4-3-5 全擺幅緩衝器 73
4-3-6 相位頻率比較器 74
4-3-7 電荷幫浦 80
4-3-8 迴路濾波器 83
4-4 量測與模擬結果 87
4-5 結果與討論 97
第五章結論 99
5-1 結論 99
5-2 未來方向 101
參考文獻 102

參考文獻

[1] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998.
[2] J. Groszkowski, “The interdependence of frequency variation and harmonic content, and the problem of constant-Frequency oscillators,” Proc. IRE, vol. 21, no. 7, pp. 958-981, July 1933.
[3] E. Hegazi, H. Sjoland and A. A. Abidi, “A filtering technique to lower LC oscillator phase noise,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1921-1930, Dec. 2001.
[4] D. Murphy, H. Darabi and H. Wu, “Implicit common-mode resonance in LC oscillators,” IEEE J. Solid-State Circuits, vol. 52, no. 3, pp. 812-821, March 2017.
[5] M. Babaie and R. B. Staszewski, “A Class-F CMOS oscillator,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 3120-3133, Dec. 2013.
[6] M. Babaie and R. B. Staszewski, “An ultra-low phase noise Class-F2 CMOS oscillator with 191 dBc/Hz FoM and long-term reliability,” IEEE J. Solid-State Circuits, vol. 50, no. 3, pp. 679-692, March 2015.
[7] M. Shahmohammadi, M. Babaie and R. B. Staszewski, “A 1/f noise upconversion reduction technique for voltage-biased RF CMOS oscillators,” IEEE J. Solid-State Circuits, vol. 51, no. 11, pp. 2610-2624, Nov. 2016.
[8] Huijung Kim, Seonghan Ryu, Yujin Chung, Jinsung Choi and Bumman Kim, “A low phase-noise CMOS VCO with harmonic tuned LC tank,” IEEE Trans Microw. Theory Techn., vol. 54, no. 7, pp. 2917-2924, July 2006.
[9] J. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE J. Solid-State Circuits, vol. 35, no. 9, pp. 1368-1382, Sept. 2000.
[10] A. Bevilacqua, F. P. Pavan, C. Sandner, A. Gerosa and A. Neviani, “Transformer-based dual-mode voltage-controlled oscillators,” IEEE Trans. Circuits Syst. II, vol. 54, no. 4, pp. 293-297, April 2007.
[11] A. Goel and H. Hashemi, “Frequency switching in dual-resonance oscillators,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 571-582, March 2007.
[12] Y. Peng et al., “A harmonic-tuned VCO with an intrinsic-high-Q F23 inductor in 65-nm CMOS, ” IEEE Microwave and Wireless Components Letters, vol. 30, no. 10, pp. 981-984, Oct. 2020.
[13] M. Shahmohammadi, M. Babaie and R. B. Staszewski, “Tuning range extension of a transformer-based oscillator through common-mode colpitts resonance,” IEEE Trans. Circuits Syst. I, vol. 64, no. 4, pp. 836-846, April 2017.
[14] C. Wan, T. Xu, X. Yi and Q. Xue, “A current-reused VCO with inductive-transformer feedback technique, ” IEEE Transactions on Microwave Theory and Techniques, vol. 70, no. 5, pp. 2680-2689, May 2022.
[15] C. Lim, J. Yin, P. Mak, H. Ramiah and R. P. Martins, “An inverse-Class-F CMOS VCO with intrinsic-high-Q 1st- and 2nd-harmonic resonances for 1/f2-to-1/f3 phase-noise suppression achieving 196.2 dBc/Hz FOM,” in IEEE Int. Solid-State Circuits Conf. (ISSCC), San Francisco, CA, 2018, pp. 374-376.
[16] A. Mazzanti and P. Andreani, "A push–pull Class-C CMOS VCO," IEEE J. Solid-State Circuits, vol. 48, no. 3, pp. 724-732, March 2013.
[17] A. Mazzanti and P. Andreani, "Class-C harmonic CMOS VCOs, with a general result on phase noise," IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2716-2729, Dec. 2008.
[18] L. Fanori and P. Andreani, "Highly efficient Class-C CMOS VCOs, including a comparison with Class-B VCOs," IEEE J. Solid-State Circuits, vol. 48, no. 7, pp. 1730-1740, July 2013.
[19] S. L. Jang and J. J. Wang, "Low-phase noise Class-C VCO with dynamic body bias," Electronics Letters, vol. 53, no. 13, pp. 847-849, 6 22 2017.
[20] R. Martins et al., "Design of a 4.2-to-5.1 GHz ultralow-power complementary Class-B/C hybrid-mode VCO in 65-nm CMOS fully supported by EDA Tools," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 11, pp. 3965-3977, Nov. 2020.
[21] S. L. Jang and Y. C. Lin, "Low-power three-path inductor Class-C VCO without any dynamic bias circuit," Electronics Letters, vol. 53, no. 17, pp. 1186-1188, 8 17 2017.
[22] H. Notani, H. Kondoh and Y. Matsuda, "A 622-MHz CMOS phase-locked loop with precharge-type phase frequency detector," Proceedings of 1994 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, 1994, pp. 129-130.
[23] W. Chen, M. E. Inerowicz, and B. Jung, "Phase frequency detector with minimal blind zone for fast frequency acquisition," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 12, pp. 936-940, 2010.
[24] Geum-Young Tak, Seok-Bong Hyun, Tae Young Kang, Byoung Gun Choi and Seong Su Park, "A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications," IEEE Journal of Solid-State Circuits, vol. 40, no. 8, pp. 1671-1679, Aug. 2005.
[25] B. Razavi, "Jitter-Power Trade-Offs in PLLs," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 4, pp. 1381-1387, April 2021.
[26] S. Min, T. Copani, S. Kiaei and B. Bakkaloglu, “A 90-nm CMOS 5-GHz ring-oscillator PLL with delay-discriminator-based active phase-noise cancellation,” IEEE J. Solid-State Circuits, vol. 48, no. 5, pp. 1151-1160, May 2013.
[27] W. Chiu, Y. Huang and T. Lin, “A 5GHz phase-locked loop using dynamic phase-error compensation technique for fast settling in 0.18-µm CMOS,” in Symposium on VLSI Circuits, Kyoto, Japan, 2009, pp. 128-129.
[28] C. Lu, H. Hsieh and L. Lu, “A low-power quadrature VCO and its application to a 0.6-V 2.4-GHz PLL,” IEEE Trans. Circuits Syst. I, vol. 57, no. 4, pp. 793-802, April 2010.
[29] Y. Chen, Y. Yu and Y. E. Chen, “A 0.18-μm CMOS dual-band frequency synthesizer with spur reduction calibration,” IEEE Microwave and Wireless Components Letters, vol. 23, no. 10, pp. 551-553, Oct. 2013.
[30] Y. -F. Kuo, M. -H. Yang and Y. -C. Chiang, “A 5-GHz adjustable loop bandwidth frequency synthesizer with an on-chip loop filter array,” IEEE Microwave and Wireless Components Letters, vol. 31, no. 1, pp. 72-75, Jan. 2021.
[31] B. Razavi, Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture Level. Cambridge University Press, 2020.
[32] X. Gao, E. A. M. Klumperink, M. Bohsali and B. Nauta, “A low noise sub-sampling PLL in which divider noise is eliminated and PD/CP noise is not multiplied by N2,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3253-3263, Dec. 2009.
[33] Z. Zhang, G. Zhu and C. Patrick Yue, “A 0.65-V 12–16-GHz sub-sampling PLL with 56.4-fsrms integrated jitter and −256.4-dB FoM,” IEEE J. Solid-State Circuits, vol. 55, no. 6, pp. 1665-1683, June 2020.
[34] D. Lee and P. P. Mercier, “AMASS PLL: An active-mixer-adopted sub-sampling PLL achieving an FOM of −255.5dB and a reference spur of −66.6dBc,” in IEEE Symposium on VLSI Circuits, Honolulu, HI, 2018, pp. 181-182.
[35] W. Chang, P. Huang and T. Lee, “A fractional-N divider-less phase-locked loop with a subsampling phase detector,” IEEE J. Solid-State Circuits, vol. 49, no. 12, pp. 2964-2975, Dec. 2014.
[36] 劉深淵，楊清淵，鎖相迴路，滄海書局，民國一百年。
[37] 詹凱鈞,“Implementations on C-band CMOS low phase noise Class-C voltage controlled oscillator, transformer-coupled quadrature voltage controlled oscillator, C-band integer-N phase locked loop with Class-F voltage controlled oscillator and X-band III-V power oscillators,” 碩士，電機工程學系，國立中央大學，2018.
[38] 莊志成, “Implementations on X-Band CMOS quadrature voltage controlled oscillator, integer-N phase locked loop and GaN high power and high efficiency voltage controlled oscillator,” 碩士，電機工程學系，國立中央大學，2019.
[39] 蔡承翰, “Implementations on CMOS C-band Class-F, S-band inverse-Class-F voltage control oscillators, and C-band sub-sampling phase-locked-loop,” 碩士，電機工程學系，國立中央大學, 2020.

指導教授

邱煥凱(Hwann-Kaeo Chiou)

審核日期

2022-8-26

推文