一個操作在2.4GHz且可調整頻寬的次取樣鎖相迴路

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姓名

盧玟廷(Wen-Ting Lu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

一個操作在2.4GHz且可調整頻寬的次取樣鎖相迴路
(A 2.4 GHz Sub-Sampling Phase-Locked Loop with Bandwidth Adjustment)

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至系統瀏覽論文 (2027-7-31以後開放)

摘要(中)

時脈產生器設計的考量項目圍繞在效能、功耗與面積上。使用LC振盪器的時脈產生器具有良好的相位雜訊表現，但需要較大的面積，而使用環型振盪器的時脈產生器其相位雜訊表現較差，但所需的面積較少。本論文欲達到擁有較小的面積的目標，故採用環型振盪器做為鎖相迴路的高頻時脈來源。為了抑制環型振盪器的相位雜訊，將透過加大頻寬來改善其表現。
傳統的鎖相迴路在加大頻寬的同時也意味著頻寬內相位雜訊的增加，所以加大頻寬對整體的相位雜訊改善有限。而次取樣鎖相迴路藉由次取樣技巧降低頻寬內的相位雜訊，因此加大頻寬對整體的相位雜訊改善較大。
本論文提出一個使用調整次取樣相位偵測器與充電幫浦的增益，藉此改變頻寬的次取樣鎖相迴路，透過調整增益得到抖動、相位雜訊與參考突波的最佳值。使用TSMC 90 nm 1P9M之CMOS製程實現，電路操作電壓為1 V，輸出頻率為2.4 GHz，功率消耗為3.05 mW。在次取樣充電幫浦增益最大的狀況下，方均根抖動為2.39 ps，相位雜訊在1 MHz的位置為 -103.9 dBc/Hz，晶片面積為0.80 mm2，其中核心電路面積為0.018 mm2。

摘要(英)

The design of clock generator is focus on its performance, power consumption, and area. The oscillator is the high frequency clock source of the phase-locked-loop (PLL), which dominate the performance. The LC tank oscillator have better phase noise than the ring oscillator but its area large too. The thesis adopts the ring oscillator-based PLL to achieve the aim of small area. Increasing the bandwidth so as to suppress the phase noise of the ring oscillator.
The typical PLL extend its bandwidth means increase its in-band noise too. As the results, extend the bandwidth of the typical PLL is minuscule to suppress the phase noise overall. However, the sub-sampling PLL have decrease its in-band noise by sub-sampling technique. Thus, extend the bandwidth of sub-sampling PLL (SSPLL) have improve the performance of phase noise.
The thesis implements a SSPLL that achieves the bandwidth change by adjusting the gain of the sub-sampling phase detector and charge pump. By adjusting the gain, the optimal value of jitter, phase noise and reference spur can be tradeoff. The chip implemented by TSMC 90 nm 1P9M CMOS process. The supply voltage is 1V of this chip, which has 2.4 GHz output frequency, and power consumption 3.05 mW. Under the condition of maximum sub-sampling charge pump gain, the rms jitter is 2.39 ps, the phase noise is -103.9 dBc/Hz at 1 MHz. The die area is 0.80 mm2 and which the active core area is 0.018 mm2.

關鍵字(中)

★ 次取樣鎖相迴路

關鍵字(英)

★ Sub-Sampling Phase-Locked Loop

論文目次

摘要 i
Abstract ii
誌謝 iii
目錄 iv
圖目錄 vi
表目錄 x
第1章緒論 1
1.1 研究動機 1
1.2 章節簡介 1
第2章電荷幫浦鎖相迴路與次取樣鎖相迴路 3
2.1 電荷幫浦鎖相迴路介紹與分析 3
2.1.1 相位頻率偵測器 4
2.1.2 電荷幫浦 5
2.1.3 迴路濾波器 6
2.1.4 電壓控制振盪器 6
2.1.5 除頻器 8
2.2 電荷幫浦鎖相迴路系統分析 8
2.3 次取樣鎖相迴路介紹與分析 11
2.3.1 次取樣相位偵測器與充電幫浦 12
2.3.2 脈衝器 13
2.4 次取樣鎖相迴路系統分析 14
2.5 鎖相迴路與次取樣鎖相迴路雜訊分析 15
2.6 討論與比較 18
第3章一個操作在2.4 GHz且可調整頻寬的次取樣鎖相迴路設計與實現 21
3.1 鎖頻迴路 22
3.1.1 相位頻率偵測器 22
3.1.2 死區產生器 23
3.1.3 低通濾波器 25
3.1.4 電荷幫浦 26
3.1.5 電壓控制振盪器 28
3.1.6 除頻器 30
3.2 次取樣鎖相迴路 31
3.2.1 次取樣相位偵測器 31
3.2.2 充電幫浦 32
3.2.3 脈波產生器 33
3.3 模擬結果 34
第4章晶片佈局與量測考量 40
4.1 晶片佈局 40
4.2 腳位說明 41
4.3 量測考量 42
第5章結論 46
5.1 規格比較 46
5.2 結論 48
5.3 未來發展 48
參考文獻 50

參考文獻

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2022-9-22

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