8T 靜態隨機存取記憶體之內積運算引擎的老化威脅緩解策略:  從架構及運算角度來提出解決的方法

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姓名

王啓旭(Chi-Hsu Wang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

8T 靜態隨機存取記憶體之內積運算引擎的老化威脅緩解策略: 從架構及運算角度來提出解決的方法
(Relieving Aging Threats on 8T-SRAM Dot-Product Engine: Approaches from Structural and Operational Perspectives)

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★ 一個可靠的靜態隨機存取記憶體內運算結構: 設計指南與耐老化策略研究	★ 一個高效的老化偵測器部屬策略: 基於生成對抗網路的設計方法
★ 考慮電壓衰退和繞線影響以優化電路時序之電源供應網絡精煉策略	★ 適用於提高自旋轉移力矩式磁阻隨機存取記憶體矩陣可靠度之老化偵測與緩解架構設計
★ 用於響應穩定性的老化感知平行掃描鏈PUF設計	★ 8T靜態隨機存取記憶體運算的老化檢測和容忍機制：適用於邏輯和 MAC 運算的應用
★ 使用擺置後的設計特徵及極限梯度提升演算法預測繞線後的繞線需求

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至系統瀏覽論文 (2027-9-23以後開放)

摘要(中)

范紐曼架構 (von Neumann architecture, VNA) 是現今大多數數位運算的基本架構，它將運算單元跟儲存單元分開，但這個架構在遇到需要相當大量資料運算應用的時候，例如影像處理或是密碼學運算，會有大量的資料在運算單元及儲存單元之間密集的傳輸，這會因為頻寬的限制而導致著名的
范紐曼瓶頸。記憶體內運算 (Computing in-memory, CIM)，已經被認為是其中一個非常有效率解決范紐曼瓶頸的方法，透過直接在記憶體內就進行運算，來省去大量的資料傳輸。在過去的研究中，已經有許多記憶體內運算的架構被提出，其中過去的研究者提出了以靜態隨機存取記憶體 (Static Random Access Memory, SRAM) 為基礎，使用 8T SRAM 的架構同時藉由類比電壓的充放電來完成多位元的點積運算架構及運算方法。此架構雖然能成功進行點積運算，但這樣的設計對於 IC 製程、電壓、溫度等變因 (PVT variation) 及老化效應 (Aging Effects) 這些因素非常敏感，這裡提到的老化效應包括偏壓不穩定性 (Bias Temperature Instability,BTI) 及熱載子注入效應 (Hot Carrier Injection, HCI)。為了提供一個可靠的CIM 多位元點積運算架構，在本篇論文中，我們提出一個考慮老化的 CIM老化偵測及兩個透過進行架構上及運算環境上的調整而達成的抗老化方式的策略指南。我們對記憶體使用動態電壓調整 (Dynamic Voltage Scaling, DVS)及補充電阻 (Supplemental Resistor, SR)兩個方式去補償因老化而下降的電流。實驗結果顯示我們所提出的方法可以使得系統維持運作的正確性且在消耗 1.13 倍的能量下壽命可以延長為兩倍。

摘要(英)

Nowadays, von Neumann architecture (VNA) has been considered as the fundamental architecture of nearly all digital computers, and the separated computing logic and the storage area is a characteristic of von Neumann architecture. In the data-intensive applications such as image recognition or
cryptography computations, large amount of data is transferred between memory and the computing cores, which causes a well-known von Neumann bottleneck due to the limitation of communication bandwidth.Computing In-Memory (CIM), which directly performs in-situ operations at
memory, has been considered as one of the promising solutions to overcome von Neumann bottleneck. There are lots of CIM structures have been proposed and studied. Previous researchers have proposed an 8T SRAM based CIM architecture
to perform multi-bit dot product computations by analog charging/discharging operations.However, such a structure is very sensitive to process variations as well as aging effects such as Bias Temperature Instability (BTI) and/or Hot Carrier Injection (HCI). In order to overcome the influence of process variations and aging effects, in this paper we propose an aging-aware computing in-memory
framework which consists of an aging detection method and two aging tolerance techniques. Specifically, we apply Dynamic Voltage Scaling (DVS) and Supplemental Resistor (SR) on CIM structure to compensate the current drop due
to aging effects. Experimental results show that we can maintain the accuracy of operation and double the system lifetime with only 1.13x power consumption in
average.

關鍵字(中)

★ 記憶體內運算
★ 正偏壓溫度不穩定性
★ 熱載子注入效應
★ 補充電阻
★ 靜態隨機存取記憶體
★ 抗老化方式

關鍵字(英)

★ computing in-memory
★ PBTI
★ HCI
★ Supplemental Resistor
★ SRAM
★ Aging Tolerance Method

論文目次

Table of Contents
摘要.................................................................................................................i
Abstract..........................................................................................................iii
致謝...............................................................................................................iv
Table of Contents...........................................................................................vi
Table of Figures...........................................................................................viii
Table of Tables................................................................................................ x
Chapter 1 Introduction................................................................................ 1
1.1 Bottleneck of Conventional Von-Neumann Architecture ................ 1
1.2 Computing In-memory..................................................................... 2
1.3 Reliability and Robustness............................................................... 6
1.4 Contributions.................................................................................... 6
Chapter 2 Preliminaries.............................................................................. 9
2.1 Basic Operation of 6T SRAM.......................................................... 9
2.2 8T SRAM Computing In-memory ................................................. 10
2.3 Aging Effect and Aging Model ...................................................... 12
2.4 Aging Estimation Under Different Operating Voltages ................. 14
2.5 Aging Effect on 8T SRAM Computing In-Memory Architecture . 15
Chapter 3 Problem Formulation............................................................... 17
Chapter 4 Framework............................................................................... 18
4.1 Derive the Precise Linear Region................................................... 18
vii
4.2 Overview of Aging-aware Operation Framework.......................... 19
4.3 Aging Detection Method ................................................................ 20
4.4 Aging Tolerance Method with Dynamic Voltage Scaling.............. 23
4.5 Aging Tolerance Method with Supplemental Resistor................... 26
4.6 Summaries for Design Guidelines ................................................. 31
Chapter 5 Experimental Results............................................................... 32
5.1 Derive the Precise Linear Region................................................... 32
5.2 Aging Tolerance Method with Dynamic Voltage Scaling.............. 34
5.3 Aging Tolerance Method with Supplemental Resistor................... 37
Chapter 6 Conclusions.............................................................................. 41

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指導教授

陳聿廣

審核日期

2022-9-23

推文