微小化雙頻阻抗匹配網路於雙頻放大器設計之應用

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姓名

周靖軒(Jing-Xuan Chou) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

微小化雙頻阻抗匹配網路於雙頻放大器設計之應用
(Design of dual-band amplifiers using miniature dual-band impedance matching network)

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至系統瀏覽論文 (2027-9-8以後開放)

摘要(中)

本研究使用以雙頻橋式T線圈為基礎之微小化雙頻阻抗匹配網路，實現可同時於2.45 / 5.5 GHz操作之雙頻低雜訊放大器與雙頻功率放大器，期能應用於IEEE 802.11 WLAN系統之2.4和5 GHz頻帶。首先，雙頻低雜訊放大器使用cascode架構搭配源極退化電感，並以雙頻阻抗匹配電路在兩頻率同時達成雜訊與阻抗匹配。電路以TSMC 0.18-μm CMOS與AFS Corp. IPD覆晶異質整合製程實現，整體電路面積為2.85 mm × 1.75 mm。在2.45 / 5.5 GHz之實測小訊號增益為15.6 / 12.1 dB，輸入、輸出反射係數皆大於10 dB，雜訊指數為2.6 / 2.8 dB，IP1dB為-18 / -14 dBm，IIP3為-5.5 / -2 dBm，於1.8 V之VDD下，功耗為11.9 mW。其次，雙頻功率放大器操作於Class-AB模式，並採用雙頻阻抗匹配電路於兩頻率達到最大功率輸出。電路以WIN 0.15-μm pHEMT GaAs製程實作，晶片面積為2.5 mm × 2.0 mm。在2.45 / 5.5 GHz之實測輸入反射損耗為11.9 / 11.9 dB，小訊號增益為12.9 / 9.3 dB，Psat為24.3 / 24.6 dBm，PAE峰值為31.4 / 32.6 %。而在以IEEE 802.11ac系統之16-QAM調變訊號進行實測的結果方面，於符合系統EVM規格與頻譜遮罩規範下，在2.45 / 5.5 GHz之最大輸出功率為19.1 / 20.3 dBm，此時之EVM為-27.3 / -27.4 dB，ACPR則為-29.0 / -28.6 dBc。透過上述兩種雙頻放大器設計，本研究成功驗證以雙頻橋式T線圈為基礎之雙頻匹配電路的可行性。

摘要(英)

This study presents 2.45 / 5.5 GHz concurrent dual-band low-noise amplifier (LNA) and dual-band power amplifier (PA) designs that employ dual-band bridge-T coil-based miniature dual-band impedance matching network. The proposed concurrent dual-band amplifiers are targeted for application in the 2.4- and 5-GHz bands of the IEEE 802.11 WLAN system. First, the proposed dual-band LNA adopts the cascode common source inductive degeneration topology, and dual-band impedance matching circuits are employed to achieve simultaneous noise and impedance matching at two operation frequencies. The proposed 2.45 / 5.5-GHz dual-band LNA is implemented through the heterogeneous integration of TSMC 0.18-μm CMOS and AFS Corp. integrated passive device (IPD) technologies, and the overall circuit size is 2.85 mm × 1.75 mm. At 2.45 / 5.5 GHz, the measured small signal gain is 15.6 / 12.1 dB, the measured input and output return loss are better than 10 dB, the measured noise figure is 2.6 / 2.8 dB, while the measured input P1dB and input IP3 are -18 / -14 dBm and -5.5 / -2 dBm, respectively. The measured power consumption under a VDD of 1.8 V is 11.9 mW. Next, the proposed dual-band PA is operated in the class-AB mode, and it utilizes dual-band impedance matching circuits to achieve maximal output power delivery at the two operation frequencies. The proposed 2.45 / 5.5-GHz dual-band PA is implemented in WIN 0.15-μm pHEMT GaAs technology, and the chip area is 2.5 mm × 2.0 mm. The measurement output power is 24.3 / 24.6 dBm while the peak power added efficiency (PAE) is 31.4 / 32.6 % at 2.45 / 5.5 GHz. The measured small signal gain and input return loss are 12.9 / 9.3 dB and 11.9 / 11.9 dB at 2.45 / 5.5 GHz, respectively. Under the IEEE 802.11ac EVM and transmit spectrum mask specifications, the maximum output power for 16-QAM modulation is 19.1 / 20.3 dBm, while the EVM and ACPR are -27.3 / -27.4 dB and -29.0 / -28.6 dBc, respectively. Through these two dual-band amplifier design examples, this study proves the feasibility of dual-band bridge-T coils for dual-band impedance matching network designs.

關鍵字(中)

★ 雙頻
★ 低雜訊放大器
★ 功率放大器
★ 阻抗匹配
★ 異質整合
★ 砷化鎵

關鍵字(英)

★ dual-band
★ low-noise amplifier
★ power amplifier
★ impedance matching
★ heterogeneous integration
★ GaAs

論文目次

摘要 i
Abstract ii
誌謝 iv
目錄 v
圖目錄 vii
表目錄 xii
第一章緒論 1
1.1 研究動機 1
1.2 文獻回顧 2
1.3 章節介紹 3
第二章微小化雙頻阻抗匹配網路 5
2.1 雙頻橋式T線圈 5
2.2 雙頻阻抗匹配網路 8
2.3 小結 13
第三章雙頻低雜訊放大器 14
3.1 電路製程 15
3.2 電路架構設計 18
3.2.1 主要架構 18
3.2.2 雙頻阻抗匹配網路 25
3.3 電路佈局設計與電磁模擬 30
3.3.1 T18 (CMOS)晶片 30
3.3.2 GIPD (IPD)晶片 33
3.3.3 T18與GIPD晶片覆晶整合 44
3.4 電路實作與量測 51
3.5 結果與討論 58
第四章雙頻功率放大器 60
4.1 電路製程 61
4.2 電路架構設計 61
4.2.1 主要架構 61
4.2.2 雙頻阻抗匹配網路 68
4.3 電路佈局設計與電磁模擬 73
4.4 電路實作與量測 104
4.4.1 連續波量測 105
4.4.2 調變訊號量測 114
4.5 結果與討論 134
第五章總結與未來展望 136
參考文獻 138

參考文獻

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指導教授

林祐生(Yo-Shen Lin)

審核日期

2022-9-29

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