| 摘要(英) |
Physical Unclonable Function (PUF) has been widely researched as potential security primitive. For applications in the field of hardware security, we expect to obtain the unclonable and unexpected responses that usually served as secret keys or unique IDs in various application scenarios. There are many kinds of PUF for the hardware circuitry, such as Arbiter PUF, Butterfly PUF, Ring-Oscillator PUF, SRAM PUF, Parallel Scan-Chain PUF, and so on.
Most existing PUF designs are independent of the original circuit. The extra circuitry for the PUF not only makes it vulnerable to removal attack but also causes high resource overhead. To prevent the above disadvantages, delay-based “Parallel Scan-Chain PUF” is proposed to solve these problems. It is implemented with an arbiter to compare the delay of two different paths of the Scan-Chain, which is a standard DFT structure built on the original circuit. However, this kind of PUF will be severely affected by aging effects, such as NBTI, PBTI, and HCI, due to the conditions of different inputs between two Scan Flip-Flop in normal mode. These will cause the original response to be flipped and eventually lead to errors, resulting in high Error Correction Code (ECC) complexity and overhead.
In this thesis, it is proposed a novel method to overcome the effects of aging and enhance reliability. To achieve the desired goal, we analyze the structure of Parallel Scan-Chain PUF and find out the possible causes of error due to aging effects. Next, we use the proposed aging compensator to mutually offset the delay between two different Scan Flip-Flops after aging. Also, we combine the signal gating for the arbiter can not only prevent it from unbalanced aging effects but also save power consumption. Experimental results show that the proposed method can reduce the responses from an average error rate of 39.96% to less than 7.5% within 10 years. Moreover, with the complexity of ECC reduced, it offers ~8x overhead reduction for the BCH encoder and decoder. |
| 參考文獻 |
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[14] Mohammad Saber Golanbari, Mojtaba Ebrahimi, Saman Kiamehr & Mehdi B. Tahoori: “Selective Flip-Flop Optimization for Reliable Digital Circuit Design”, 2020 TCAD
[15] Atousa Jafari, Mohsen Raji, Behnam Ghavami: “Timing Reliability Improvement of Master-Slave Flip-Flops in the Presence of Aging Effects”, 2020 TCSI
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