基於電阻式記憶體之運算記憶體測試

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姓名

楊育丞(Yu-Cheng Yang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

基於電阻式記憶體之運算記憶體測試
(Testing of RRAM-based Computing-In-Memories)

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至系統瀏覽論文 (2028-2-1以後開放)

摘要(中)

現代馮紐曼(von Neumann)計算架構在運算(computing)單元與記憶體單元間的資料傳輸成為資料密集型(data-intensive)應用中系統性能與能耗的瓶頸。記憶體內運算(CIM)架構被認為是克服該瓶頸的一個選擇。CIM具有儲存和運算的功能。電阻式隨機存取記憶體(RRAM)是其中一種非揮發性記憶體，它被認為是實現CIM的一個好的選擇。在這篇論文中，我們提出基於RRAM之運算記憶體故障建模及測試包含了記憶體和邏輯運算。首先，藉由插入細胞內(intra-cell)和細胞間(inter-cell)的電性缺陷(electrical defect)對基於1T1R RRAM的CIM記憶體進行了故障建模(fault modeling)。定義了幾個新的故障，包括運算故障和相反樣式相依(complement-pattern-dependent)的故障。此外，在word-oriented記憶體中，故障可分為字內(intra-word)和字間(inter-word)故障。然後，通過考慮字內故障和字間故障，分別提出了6N的March測試與10N的March測試。為了能夠產生出運算和記憶體故障的測試演算法，提出了一種用於CIM記憶體的測試演算法生成(test algorithm generation)方法。CIM記憶體的測試演算法生成方法可以通過檢查運算故障的運算元來減少生成的時間。測試演算法中的運算元在故障模擬前被檢查可以消除許多冗餘的測試演算法。最後，由於基於1T1R RRAM的CIM記憶體故障建模結果，我們關注到電阻分佈重疊的問題。為了克服這個問題，我們提出了一個新的架構，並且可以擴展到多個運算元的操作。同時，對於這個架構進行了測試和故障建模。介紹了一些新的運算故障。通過考慮字內故障和字間故障，分別提出了9N March測試和12N March測試，以涵蓋新架構定義的故障。

摘要(英)

The data movement between the computing unit and memory unit of modern von Neumann computing architecture becomes a bottleneck of system performance and energy consumption for data intensive applications. Computing-in-memory (CIM) architecture is considered as an alternative to overcome the bottleneck. A CIM has the function of memory and computing. Resistive random access memory (RRAM) is one of nonvolatile memories, which is considered as a good candidate for the implementation of CIMs. In this thesis, we propose fault modeling and testing techniques for RRAM-based CIMs with memory and logic operations. Firstly, fault modeling for 1T1R RRAM-based CIMs is executed by injecting intra-cell and inter-cell electrical defects. Several new faults are defined, including computing faults and complement-pattern-dependent faults. Also, the faults can be divided into intra-word and inter-word faults for word-oriented memory. Then, a 6N March test and a 10N March test are proposed by considering intra-word faults and inter-word faults, respectively. A test algorithm generation method for CIM memories is proposed to generate test algorithm for computing and memory faults as well. The test algorithm generation method for CIM memories can reduce generation time by checking the operands of computing faults. The operands in test algorithms are checked before fault simulation, which can eliminate many redundant test algorithms. Finally, we focus on the issue which is the overlap of resistance distribution due to the result of fault modeling for 1T1R RRAM-based CIMs. To overcome this issue, a new architecture is proposed and it can be extended to multi-operand operation. Also, the testing and fault modeling of this architecture are performed. Some new computing faults are introduced. A 9N March test and a 12N March test are proposed by considering intra-word faults and inter-word faults to cover the defined faults of new architecture, respectively.

關鍵字(中)

★ 記憶體內運算
★ 電阻式隨機存取記憶體
★ 記憶體測試
★ 測試演算法生成

關鍵字(英)

★ Computing-In-Memories
★ Resistive Random Access Memory
★ Memory Testing
★ Test Algorithm Generation

論文目次

1 Introduction 1
1.1 Resistive Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 RRAM-based Computing-In-Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Testing of Computing-In-Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Motivation and Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.5 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Testing of 1T1R-RRAM-based Computing-In-Memories 9
2.1 1T1R-RRAM CIMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Fault Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1 Defects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.2 Fault Modeling Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.3 Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3 Faults in Computing Mode and Memory Mode . . . . . . . . . . . . . . . . . . . . . 21
2.4 Defect Sensitivity with respect to Functional Operations . . . . . . . . . . . . . . . . 22
2.4.1 Two-operand Logic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4.2 Multi-operand Logic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5 Test Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.5.1 Existing Fault Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.5.2 Computing Faults and Pattern Dependent Faults . . . . . . . . . . . . . . . . 29
2.5.3 Fault Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.5.4 Test Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3 Test Algorithm Generation for CIMs 45
3.1 Test Algorithm Generation by Simulation . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.1.1 Test Algorithm Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.1.2 Fault Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.2 Test Algorithm Generation of CIMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.2.1 Fault Descriptor of New Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.2.2 Test Algorithm generation Strategy . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3 Test Algorithm Generation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.4 The Result of Test Algorithm Generation . . . . . . . . . . . . . . . . . . . . . . . . . 58
4 Testing of Enhanced 1T1R-RRAM-based CIMs 65
4.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.2 Enhanced Scouting Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.3 1T1R ESL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.4 Defect Sensitivity with respect to Functional Operations for 1T1R ESL . . . . . . . . 69
4.5 Extra Defects and Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.6 Test Development for 1T1R ESL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.6.1 Fault Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.6.2 Test Algorithm for 1T1R ESL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5 Conclusion and Future Work 81
5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

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指導教授

李進福(Jin-Fu Li)

審核日期

2023-2-2

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