博碩士論文 107324013 詳細資訊




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姓名 邱重宇(Chung-Yu Chiu)  查詢紙本館藏   畢業系所 化學工程與材料工程學系
論文名稱 退火過程之外加壓應力對電鍍銅微結構演變機制研究
(The external compression stress effect on microstructure evolution of electroplated Cu during annealing process)
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摘要(中) 熱壓鍵合(TCB)是半導體先進封裝製程中常用的技術,透過在製程中施加外加應力來增加兩界面的接觸面積,並藉由溫度驅使兩界面的原子交互擴散,藉此消除界面來達到晶圓鍵合。鍵合後的接點之機械性質與其微結構有關,然而,大多文獻都只有討論溫度效應對於微結構的影響,對於熱壓鍵合製程中施加的外加應力對於接點微結構影響的討論十分有限,因此,我們嘗試研究外加應力在熱壓鍵合過程中對微結構的影響,藉由在電鍍銅退火過程中施加單軸應力去模擬TCB製程,並透過施加不同的外加單軸應力來觀察微結構隨外加應力的變化,藉此討論單軸外加應力於熱壓鍵合製程中對電鍍銅層微結構的影響。
在第四章節中,我們發現電鍍銅的微結構會隨著退火過程中施加的外加應力產生變化,其中,又以在較低溫373K變化最顯著。藉由晶粒尺寸分布的分析發現,外加應力的施加會改變電鍍銅的生長模式,使其由正常晶粒生長模式轉變為異常晶粒生長模式。透過對異常生長晶粒的晶面取向分析,發現生成的異常晶粒並無特定晶面取向。在第五章中透過穿透式電子顯微鏡(TEM)分析於外加應力作用下退火的電鍍銅微結構發現,在異常生長晶粒及其他小晶粒區域的交界處產生許多由差排構成的次晶界。透過上述分析結果以及討論,本研究提出了在退火製程中施加外加應力效應對於電鍍銅微結構的變化機制。
摘要(英) Thermal compression bonding (TCB) was one of frequently used technique in semiconductor packaging process. In TCB technique, the purpose of applying external stress is increasing the contact area between interface, while the elevated temperature could enhance the mobility of atoms for inter-diffusion to eliminate the interface and further accomplish bonding. The mechanical properties of joints were significantly related to their microstructure. However, most of research only focus on the effect of bonding temperature and bonding time on the microstructure. The discussion about the external stress effect on the microstructure is limited. Therefore, we would figure out the uniaxial external stress effect on the microstructure evolution of electroplated Cu films during TCB process. To simulate the thermal compression bonding process, the electroplated Cu films were stressed during thermal annealing. The external compression stress effect on microstructure of electroplated Cu films during TCB process could be discussed by the observation of the difference in microstructure with applying a different level of external stress.
In chapter 4, we observed that the microstructure of electroplated Cu films changed with different level of external stress. Besides, microstructure changed by external stress most obviously in 373K. With grain size distribution analysis, we deduced that the external stress would change the grain growth mode of electroplated Cu films from normal grain growth mode to abnormal grain growth mode during thermal annealing. By analyzing the orientation of those abnormal grains, we observed that the initial generated abnormal grains reveals no preferred orientation. In chapter 5, the external stress effect on the grain growth kinetic of electroplated Cu film have been calculated. By analyzing the microstructure of annealed electroplated Cu films with external stress through transmission electron microscope (TEM), subgrain boundaries were comprised of dislocations which generated at the interface of abnormal grains and fine grains. From the analysis results and discussion, this research proposed the mechanism of uniaxial external stress effect on the microstructure evolution of electroplated Cu films during thermal annealing process.
關鍵字(中) ★ 熱壓鍵合
★ 外加應力效應
★ 退火過程
★ 微結構演變
關鍵字(英) ★ thermal compression bonding
★ external stress effect
★ annealing process
★ microstructure evolution
論文目次 中文摘要 i
Abstract ii
Table of Contents v
List of Figures vi
List of tables viii
Chapter 1: Introduction 1
1.1 Advanced packaging technology 1
1.2 Chip/Substrate interconnection 3
1.3 Introduction for thermal annealing 10
Chapter 2: Motivation 14
Chapter 3: Experimental 16
3.1 Sample preparing for the stressed annealed electroplated Cu films 16
3.2 The analysis of the microstructure of stressed annealed electroplated Cu films 18
Chapter 4: Uniaxial external compression stress effect on Cu microstructure evolution during annealing 19
4.1 Microstructure of each external stress and annealing temperature conditions. 19
4.2 Grain growth mode analysis 23
4.3 Common reason for abnormal grain growth 26
Chapter 5: Mechanism of external stress effect on the microstructure evolution during annealing 35
5.1 External stress effect on the grain growth kinetic of electroplated Cu films 35
5.2 Intrinsic properties for electroplated Cu during annealing 38
5.3 External stress effect on electroplated Cu film during annealing 42
5.4 Subgrain boundaries enhanced abnormal grain formation 46
5.5 Microstructure evolution of annealed electroplated Cu films with and without stress 48
Chapter 6: Summary 50
Reference: 52
參考文獻 [1] Thompson, S. E., & Parthasarathy, S. (2006). Moore′s law: the future of Si microelectronics. Materials today, 9(6), 20-25.
[2] Mack, C. A. (2011). Fifty years of Moore′s law. IEEE Transactions on semiconductor manufacturing, 24(2), 202-207.
[3] Li, M. Y., Su, S. K., Wong, H. S. P., & Li, L. J. (2019). How 2D semiconductors could extend Moore’s law. Nature, 567(7747), 169-170.
[4] Chen, R., Li, Y. C., Cai, J. M., & Cao, K. (2020). Atomic level deposition to extend Moore’s law and beyond. International Journal of Extreme Manufacturing, 2(2), 022002.
[5] Pirati, A., van Schoot, J., Troost, K., van Ballegoij, R., Krabbendam, P., Stoeldraijer, J., ... & Migura, S. (2017, March). The future of EUV lithography: enabling Moore′s Law in the next decade. In extreme ultraviolet (EUV) lithography VIII (Vol. 10143, pp. 57-72). SPIE.
[6] Arden, W., Brillouët, M., Cogez, P., Graef, M., Huizing, B., & Mahnkopf, R. (2010). More-than-Moore white paper. Version, 2, 14.
[7] Waldrop, M. M. (2016). More than moore. Nature, 530(7589), 144-148.
[8] Theis, T. N., & Wong, H. S. P. (2017). The end of moore′s law: A new beginning for information technology. Computing in Science & Engineering, 19(2), 41-50.
[9] England, L., & Arsovski, I. (2017, December). Advanced packaging saves the day!—How TSV technology will enable continued scaling. In 2017 IEEE International Electron Devices Meeting (IEDM) (pp. 3-5). IEEE.
[10] Farnum, C., & Rahim, K. (2021, June). Small Feature Size, Large Impact: How Advanced Packaging Will Reinvent Radar Manufacturing. In 2021 IEEE 71st Electronic Components and Technology Conference (ECTC) (pp. 1749-1753). IEEE.
[11] Kawano, M. (2021, April). Technology trends in 2.5 D/3D packaging and heterogeneous integration. In 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) (pp. 1-3). IEEE.
[12] Lau, J. H. (2022). Recent advances and trends in advanced packaging. IEEE Transactions on Components, Packaging and Manufacturing Technology, 12(2), 228-252.
[13] Zhang, X., Lin, J. K., Wickramanayaka, S., Zhang, S., Weerasekera, R., Dutta, R., ... & Kwong, D. L. (2015). Heterogeneous 2.5 D integration on through silicon interposer. Applied physics reviews, 2(2), 021308.
[14] Nayak, D. K., Banna, S., Samal, S. K., & Lim, S. K. (2015, October). Power, performance, and cost comparisons of monolithic 3D ICs and TSV-based 3D ICs. In 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (pp. 1-2). IEEE.
[15] Lau, J. H. (2011, October). Evolution, challenge, and outlook of TSV, 3D IC integration and 3D silicon integration. In 2011 International symposium on advanced packaging materials (APM) (pp. 462-488). IEEE.
[16] Li, Y., Srinath, P. K. M., & Goyal, D. (2016). A review of failure analysis methods for advanced 3D microelectronic packages. Journal of Electronic Materials, 45, 116-124.
[17] Ko, C. T., & Chen, K. N. (2013). Reliability of key technologies in 3D integration. Microelectronics Reliability, 53(1), 7-16.
[18] Auersperg, J., Dudek, R., Oswald, J., & Michel, B. (2011, April). Interaction integral and mode separation for beol-cracking and-delamination investigations under 3d-ic integration aspects. In 2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (pp. 1-7). IEEE.
[19] Fujimoto, K., Nakata, S., Manabe, T., & Fujii, A. (1996). Effects of bonding conditions and surface state on bondability: Study of Cu wire stitch bonding (1st Report).
[20] Murali, S., Srikanth, N., Wong, Y. M., & Vath III, C. J. (2007). Fundamentals of thermo-sonic copper wire bonding in microelectronics packaging. Journal of Materials Science, 42(2), 615-623.
[21] Chauhan, P. S., Choubey, A., Zhong, Z., Pecht, M. G., Chauhan, P. S., Choubey, A., ... & Pecht, M. G. (2014). Copper wire bonding (pp. 1-9). Springer New York.
[22] Harman, G. (2010). Wire bonding in microelectronics. McGraw-Hill Education.
[23] Murali, S., Srikanth, N., & Vath III, C. J. (2003). An analysis of intermetallics formation of gold and copper ball bonding on thermal aging. Materials research bulletin, 38(4), 637-646.
[24] Fre´ mont, H., Dele´ tage, J. Y., Pintus, A., & Danto, Y. (2001). Evaluation of the moisture sensitivity of molding compounds of IC’s packages. J. Electron. Packag., 123(1), 16-18.
[25]Lebbai, M., Kim, J. K., & Yuen, M. M. (2003). Effects of moisture and elevated temperature on reliability of interfacial adhesion in plastic packages. Journal of electronic materials, 32, 574-582.
[26] Asai, S. I., Ando, T., & Tobita, M. (1996). Adhesion between Ni/Fe lead frame and epoxy molding compounds in IC packages. Journal of adhesion science and technology, 10(1), 1-15.
[27] Wong, C. P., Luo, S., & Zhang, Z. (2000). Flip the chip. Science, 290(5500), 2269-2270.
[28] Elenius, P., & Levine, L. (2000). Comparing flip-chip and wire-bond interconnection technologies. Chip Scale Review, 4(6).
[29] Tu, K. N., & Zeng, K. (2001). Tin–lead (SnPb) solder reaction in flip chip technology. Materials science and engineering: R: reports, 34(1), 1-58.
[30] Tu, K. N., Ku, F., & Lee, T. Y. (2001). Morphological stability of solder reaction products in flip chip technology. Journal of electronic materials, 30, 1129-1132.
[31] Liu, C. Y., Chen, C., Mal, A. K., & Tu, K. N. (1999). Direct correlation between mechanical failure and metallurgical reaction in flip chip solder joints. Journal of Applied Physics, 85(7), 3882-3886.
[32] Subramanian, K. N., Puttlitz, K. J., & Galyon, G. T. (2007). Impact of the ROHS directive on high-performance electronic systems: Part I: need for lead utilization in exempt systems. Lead-Free Electronic Solders: A Special Issue of the Journal of Materials Science: Materials in Electronics, 331-346.
[33] Puttlitz, K. J., & Galyon, G. T. (2007). Impact of the ROHS Directive on high-performance electronic systems: Part II: key reliability issues preventing the implementation of lead-free solders. Journal of Materials Science: Materials in Electronics, 18(1-3), 347-365.
[34] Suganuma, K. (2001). Advances in lead-free electronics soldering. Current Opinion in Solid State and Materials Science, 5(1), 55-64.
[35] Wu, C. M. L., Yu, D. Q., Law, C. M. T., & Wang, L. (2004). Properties of lead-free solder alloys with rare earth element additions. Materials Science and Engineering: R: Reports, 44(1), 1-44.
[36] Gayle, F. W., Becka, G., Syed, A., Badgett, J., Whitten, G., Pan, T. Y., ... & Olson, C. (2001). High temperature lead-free solder for microelectronics. Jom, 53, 17-21.
[37] Yu, D. Q., Zhao, J., & Wang, L. (2004). Improvement on the microstructure stability, mechanical and wetting properties of Sn–Ag–Cu lead-free solder with the addition of rare earth elements. Journal of alloys and compounds, 376(1-2), 170-175.
[38] Pang, J. H., Xu, L., Shi, X. Q., Zhou, W., & Ngoh, S. L. (2004). Intermetallic growth studies on Sn-Ag-Cu lead-free solder joints. Journal of Electronic Materials, 33, 1219-1226.
[39] Choubey, A., Yu, H., Osterman, M., Pecht, M., Yun, F., Yonghong, L., & Ming, X. (2008). Intermetallics characterization of lead-free solder joints under isothermal aging. Journal of Electronic Materials, 37, 1130-1138.
[40] Hwang, C. W., Kim, K. S., & Suganuma, K. (2003). Interfaces in lead-free soldering. Journal of electronic materials, 32, 1249-1256.
[41] Osório, W. R., Peixoto, L. C., Garcia, L. R., Mangelinck-Noël, N., & Garcia, A. (2013). Microstructure and mechanical properties of Sn–Bi, Sn–Ag and Sn–Zn lead-free solder alloys. Journal of Alloys and Compounds, 572, 97-106.
[42] Zuo, Y., Bieler, T. R., Zhou, Q., Ma, L., & Guo, F. (2018). Electromigration and thermomechanical fatigue behavior of Sn0. 3Ag0. 7Cu solder joints. Journal of Electronic Materials, 47, 1881-1895.
[43] Lin, Y. H., Tsai, C. M., Hu, Y. C., Lin, Y. L., & Kao, C. R. (2005). Electromigration-induced failure in flip-chip solder joints. Journal of electronic materials, 34, 27-33.
[44] Subramanian, K. N., Chae, S. H., Zhang, X., Lu, K. H., Chao, H. L., Ho, P. S., ... & Ramanathan, L. N. (2007). Electromigration statistics and damage evolution for Pb-free solder joints with Cu and Ni UBM in plastic flip-chip packages. Lead-Free Electronic Solders: A Special Issue of the Journal of Materials Science: Materials in Electronics, 247-258.
[45] Yang, D., Chan, Y. C., Wu, B. Y., & Pecht, M. (2008). Electromigration and thermomigration behavior of flip chip solder joints in high current density packages. Journal of Materials Research, 23(9), 2333-2339.
[46] Liang, Y. C., Tsao, W. A., Chen, C., Yao, D. J., Huang, A. T., & Lai, Y. S. (2012). Influence of Cu column under-bump-metallizations on current crowding and Joule heating effects of electromigration in flip-chip solder joints. Journal of Applied Physics, 111(4), 043705.
[47] Jiang, A. L. X., Ming, L. C., Gao, J. C. Y., & Hwee, T. K. (2006, August). Pillar bump technology and integrated embedded passive devices. In 2006 7th International Conference on Electronic Packaging Technology (pp. 1-5). IEEE.
[48] Gerber, M., Beddingfield, C., O′Connor, S., Yoo, M., Lee, M., Kang, D., ... & Park, K. (2011, May). Next generation fine pitch Cu Pillar technology—Enabling next generation silicon nodes. In 2011 IEEE 61st electronic components and technology conference (ECTC) (pp. 612-618). IEEE.
[49] Yoo, J. H., Kang, I. S., Jung, G. J., Kim, S., Ahn, H. S., Choi, W. H., ... & Yu, J. N. (2010, December). Analysis of electromigration for Cu pillar bump in flip chip package. In 2010 12th Electronics Packaging Technology Conference (pp. 129-133). IEEE.
[50] Hsiao, Y. H., Chen, C. F., Yang, P. F., Lee, C. C., Liu, M. C., Lin, K. L., ... & Factor, B. J. (2014, September). The physics of Cu pillar bump interconnect under electromigration stress testing. In Proceedings of the 5th Electronics System-integration Technology Conference (ESTC) (pp. 1-6). IEEE.
[51] Akiba, T., Funaya, T., Sakata, K., Tsuchiya, H., & Nakagawa, K. (2017, November). Electromigration mechanism on interconnected Cu pillar in flip chip package. In 2017 IEEE CPMT Symposium Japan (ICSJ) (pp. 1-4). IEEE.
[52] Hsiao, Y. H., & Lin, K. L. (2016). The formation and conversion of intermetallic compounds in the Cu pillar Sn–Ag micro-bump with ENEPIG Cu substrate under current stressing. Journal of Materials Science: Materials in Electronics, 27, 2201-2205.
[53] Hsiao, Y. H., Lin, K. L., Lee, C. W., Shao, Y. H., & Lai, Y. S. (2012). Study of electromigration-induced failures on Cu pillar bumps joined to OSP and ENEPIG substrates. Journal of electronic materials, 41, 3368-3374.
[54] Huang, M., Chen, L., Zhou, S., & Ye, S. (2011, October). Effect of surface finish (OSP and ENEPIG) on failure mechanism induced by electromigration in Sn-3.0 Ag-0.5 Cu flip chip solder interconnect. In 2011 International Symposium on Advanced Packaging Materials (APM) (pp. 297-301). IEEE.
[55] Zou, Y. S., Hsiao, Y. H., & Lin, K. L. (2014, December). Intermetallic compound growth mechanism and failure modes of flip chip solder bump with different UBM structure during electromigration. In 2014 IEEE 16th Electronics Packaging Technology Conference (EPTC) (pp. 155-158). IEEE.
[56] Xu, K., Fu, X., Wang, X., Fu, Z., Yang, X., Chen, S., ... & Chen, H. (2022). The effect of grain orientation of β-Sn on Copper pillar solder joints during electromigration. Materials, 15(1), 108.
[57] Tian, Y., Han, J., Ma, L., & Guo, F. (2018). The dominant effect of c-axis orientation in tin on the electromigration behaviors in tricrystal Sn-3.0 Ag-0.5 Cu solder joints. Microelectronics Reliability, 80, 7-13.
[58] Kim, Y. R., Madanipour, H., Osmanson, A. T., Tajedini, M., Kim, C. U., Thompson, P. F., & Chen, Q. (2021, June). Relationship Between the Grain Orientation and the Electromigration Reliability of Electronic Packaging Interconnects. In 2021 IEEE 71st Electronic Components and Technology Conference (ECTC) (pp. 2334-2339). IEEE.
[59] Yang, T. L., Yu, J. J., Li, C. C., Lin, Y. F., & Kao, C. R. (2015). Dominant effects of Sn orientation on serrated cathode dissolution and resulting failure in actual solder joints under electromigration. Journal of Alloys and Compounds, 627, 281-286.
[60] Lee, K., Kim, K. S., Tsukada, Y., Suganuma, K., Yamanaka, K., Kuritani, S., & Ueshima, M. (2011). Influence of crystallographic orientation of Sn–Ag–Cu on electromigration in flip-chip joint. Microelectronics Reliability, 51(12), 2290-2297.
[61] Shen, Y. A., & Wu, J. A. (2022). Effect of Sn grain orientation on reliability issues of Sn-rich solder joints. Materials, 15(14), 5086.
[62] Lu, M., Shih, D. Y., Lauro, P., Goldsmith, C., & Henderson, D. W. (2008). Effect of Sn grain orientation on electromigration degradation mechanism in high Sn-based Pb-free solders. Applied physics letters, 92(21), 211909.
[63] Huang, T. C., Yang, T. L., Ke, J. H., Hsueh, C. H., & Kao, C. R. (2014). Effects of Sn grain orientation on substrate dissolution and intermetallic precipitation in solder joints under electron current stressing. Scripta Materialia, 80, 37-40.
[64] Hsu, P. N., Lee, D. L., Tran, D. P., Shie, K. C., Tsou, N. T., & Chen, C. (2022). Effect of Tin Grain Orientation on Electromigration-Induced Dissolution of Ni Metallization in SnAg Solder Joints. Materials, 15(20), 7115.
[65] Jang, E. J., Kim, J. W., Kim, B., Matthias, T., & Park, Y. B. (2011). Annealing temperature effect on the Cu-Cu bonding energy for 3D-IC integration. Metals and Materials International, 17, 105-109.
[66] Kim, S. E., & Kim, S. (2015). Wafer level Cu–Cu direct bonding for 3D integration. Microelectronic Engineering, 137, 158-163.
[67] Ma, Y., Roshanghias, A., & Binder, A. (2018). A comparative study on direct Cu–Cu bonding methodologies for copper pillar bumped flip-chips. Journal of Materials Science: Materials in Electronics, 29, 9347-9353.
[68] Panigrahy, A. K., & Chen, K. N. (2018). Low temperature Cu–Cu bonding technology in three-dimensional integration: An extensive review. Journal of Electronic packaging, 140(1).
[69] Tan, C. S., Lim, D. F., Singh, S. G., Goulet, S. K., & Bergkvist, M. (2009). Cu–Cu diffusion bonding enhancement at low temperature by surface passivation using self-assembled monolayer of alkane-thiol. Applied Physics Letters, 95(19), 192108.
[70] Hu, L., Goh, S. C. K., Tao, J., Lim, Y. D., Zhao, P., Lim, M. J. Z., ... & Tan, C. S. (2021). Time-dependent evolution study of Ar/N2 plasma-activated Cu surface for enabling two-step Cu-Cu direct bonding in a non-vacuum environment. ECS Journal of Solid State Science and Technology, 10(12), 124001.
[71] Dubey, V., Derakhshandeh, J., Beyne, E., Gerets, C., Cooper, E., Laermans, P., ... & De Wolf, I. (2016, May). Surface treatment to enable low temperature and pressure copper direct bonding. In 2016 IEEE 66th Electronic Components and Technology Conference (ECTC) (pp. 2435-2441). IEEE.
[72] Kim, J. W., Kim, K. S., Lee, H. J., Kim, H. Y., Park, Y. B., & Hyun, S. (2011, July). The effect of plasma pre-cleaning on the Cu-Cu direct bonding for 3D chip stacking. In 18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) (pp. 1-4). IEEE.
[73] Huang, Y. P., Chien, Y. S., Tzeng, R. N., Shy, M. S., Lin, T. H., Chen, K. H., ... & Chen, K. N. (2013). Novel Cu-to-Cu Bonding With Ti Passivation at 180$^{circ}{
m C} $ in 3-D Integration. IEEE Electron Device Letters, 34(12), 1551-1553.
[74] Panigrahi, A. K., Bonam, S., Ghosh, T., Vanjari, S. R. K., & Singh, S. G. (2015, May). Low temperature, low pressure CMOS compatible Cu-Cu thermo-compression bonding with Ti passivation for 3D IC integration. In 2015 IEEE 65th Electronic Components and Technology Conference (ECTC) (pp. 2205-2210). IEEE.
[75] Huang, Y. P., Chien, Y. S., Tzeng, R. N., & Chen, K. N. (2015). Demonstration and electrical performance of Cu–Cu bonding at 150° C with Pd passivation. IEEE Transactions on Electron Devices, 62(8), 2587-2592.
[76] Huang, Y. P., Chien, Y. S., Tzeng, R. N., & Chen, K. N. (2015). Demonstration and electrical performance of Cu–Cu bonding at 150° C with Pd passivation. IEEE Transactions on Electron Devices, 62(8), 2587-2592.

[77] Yang, Y. T., Yu, T. Y., Kuo, S. C., Huang, T. Y., Yang, K. M., Ko, C. T., ... & Chen, K. N. (2017, May). Breakthrough in Cu to Cu Pillar-Concave Bonding on Silicon Substrate with Polymer Layer for Advanced Packaging, 3D, and Heterogeneous Integration. In 2017 IEEE 67th Electronic Components and Technology Conference (ECTC) (pp. 637-642). IEEE.
[78] Lin, P. F., Tran, D. P., Liu, H. C., Li, Y. Y., & Chen, C. (2022). Interfacial characterization of low-temperature Cu-to-Cu direct bonding with chemical mechanical planarized nanotwinned Cu films. Materials, 15(3), 937.
[79] Wang, Y. M., Sansoz, F., LaGrange, T., Ott, R. T., Marian, J., Barbee Jr, T. W., & Hamza, A. V. (2013). Defective twin boundaries in nanotwinned metals. Nature materials, 12(8), 697-702.
[80] Lu, T. F., Lai, T. Y., Chu, Y. Y., & Wu, Y. S. (2021). Effect of nanotwin boundary on the Cu–Cu bonding. ECS Journal of Solid State Science and Technology, 10(7), 074001.
[81] Liu, C. M., Lin, H. W., Huang, Y. S., Chu, Y. C., Chen, C., Lyu, D. R., ... & Tu, K. N. (2015). Low-temperature direct copper-to-copper bonding enabled by creep on (111) surfaces of nanotwinned Cu. Scientific reports, 5(1), 1-11.
[82] Humphreys, F. J., & Hatherly, M. (2012). Recrystallization and related annealing phenomena. elsevier.
[83] Vincent, J., Díaz-Guerra, C., Piqueras, J., Amariei, A., Polychroniadis, E. K., & Diéguez, E. (2006). Characterization of undoped and Te-doped GaSb crystals grown by the vertical feeding method. Journal of crystal growth, 289(1), 18-23.
[84] Reed-Hill, R. E., Abbaschian, R., & Abbaschian, R. (1973). Physical metallurgy principles (Vol. 17). New York: Van Nostrand.
[85] Fullman, R. L., & Fisher, J. C. (1951). Formation of annealing twins during grain growth. Journal of Applied Physics, 22(11), 1350-1355.
[86] Lannon, J., Gregory, C., Lueck, M., Huffman, A., & Temple, D. (2009, May). High density Cu-Cu interconnect bonding for 3-D integration. In 2009 59th Electronic Components and Technology Conference (pp. 355-359). IEEE.
[87] Gondcharton, P., Imbert, B., Benaissa, L., & Verdier, M. (2015, May). Copper-copper direct bonding: Impact of grain size. In 2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM) (pp. 229-232). IEEE.
[88] Frazier, W. E., Rohrer, G. S., & Rollett, A. D. (2015). Abnormal grain growth in the Potts model incorporating grain boundary complexion transitions that increase the mobility of individual boundaries. Acta Materialia, 96, 390-398.
[89] Fu, L. M., Wang, H. R., Wang, W., & Shan, A. D. (2011). Austenite grain growth prediction coupling with drag and pinning effects in low carbon Nb microalloyed steels. Materials Science and Technology, 27(6), 996-1001.
[90] Zhang, J. M., Xu, K. W., & Ji, V. (2002). Competition between surface and strain energy during grain growth in free-standing and attached Ag and Cu films on Si substrates. Applied surface science, 187(1-2), 60-67.
[91] G. B. Harris, Philosophical Magazine Series 7, 1952, vol. 43:336, pp. 113–123
[92] Suryanarayana, C., Norton, M. G., Suryanarayana, C., & Norton, M. G. (1998). X-rays and Diffraction (pp. 3-19). Springer US.
[93] Shewmon, P. (Ed.). (2016). Diffusion in solids. Springer.
[94] Gottstein, G., & Shvindlerman, L. S. (2009). Grain boundary migration in metals: thermodynamics, kinetics, applications. CRC press.
[95] Hillert, M. J. A. M. (1965). On the theory of normal and abnormal grain growth. Acta metallurgica, 13(3), 227-238.
[96] Mizera, J., Wyrzykowski, J. W., & Kurzydłowski, K. J. (1988). Description of the kinetics of normal and abnormal grain growth in austenitic stainless steel. Materials Science and Engineering: A, 104, 157-162.
[97] Edalati, K., Hashiguchi, Y., Iwaoka, H., Matsunaga, H., Valiev, R. Z., & Horita, Z. (2018). Long-time stability of metals after severe plastic deformation: Softening and hardening by self-annealing versus thermal stability. Materials Science and Engineering: A, 729, 340-348.
[98] Bonneville, J. and Escaig, B. Cross-slipping process and the stress-orientation dependence in pure copper. Acta Metall. 27, 1477 (1979).
[99] Bonneville, J; Escaig, B; and Martin, JL. A study of cross-slip activation parameters in pure copper.
Acta Metall. 36, 1989 (1988).
[100] Kuykendall, W. P., Wang, Y., & Cai, W. (2020). Stress effects on the energy barrier and mechanisms of cross-slip in FCC nickel. Journal of the Mechanics and Physics of Solids, 144, 104105.
指導教授 劉正毓(Cheng-Yi Liu) 審核日期 2023-7-3
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