2.5Gbps光纖收發機設計

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姓名

呂昭信(Chao-Hsin Lu ) 查詢紙本館藏

畢業系所

電機工程研究所

論文名稱

2.5Gbps光纖收發機設計
(2.5Gbps Optical Transceiver)

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摘要(中)

光纖網路應用在高速和長程傳輸通訊已經變成一個主要的趨勢。傳統上，光纖收發機是使用昂貴的砷化鉀製程。今日，數GHz的射頻ICs已經成功的使用次微米的CMOS和BicMOS製程來達到。而以加快降低光纖元件的成本為目標，本篇論文探討使用矽製程來達成光纖收發機的電路設計技術。以及研究的目的是為了達到2.5Gbps的光纖收發機電路。
在傳送器端，一個2伏、2.5Gbps的CMOS資料合成器被提出。高速的平行至串列的轉換是使用一個低抖動和八個相位的PLL來做以時間區分的多工器。其最大的轉換速率超過了312.5Mbytes/s。更進一步地，一個雷射驅動器被使用來驅動一個外加的雷射電晶體。其製作在0.8mm BiCMOS的製程，可達到30mA調變電流、10mA偏壓電流和操作在3Gbps下。經量測的結果，其眼圖符合OC-48的要求。
接收器的前端ICs發展在這一次的工作之中，包含了一個轉阻放大器和一個限制放大器，它們是利用0.35mm CMOS製程來達到，且操作在3V的電壓下。轉阻放大器提供一個54dBW和2.5GHz的-3dB頻寬。而限制放大器則是有4mv的敏感度、2.2GHz的-3dB頻寬和40dB的增益。另外，再提出一個使用3倍取樣技術的資料回覆器電路。
所有在這篇論文中所提出之電路皆有完整的探討和測量。其效能大大地顯視出未來光纖通訊在CMOS製程上SoC化的可行性。

摘要(英)

Optical networking has become a main stream for high speed and long haul data communication. Conventionally, optical transceivers are implemented in expensive GaAs process. Nowadays, multi-GHz RF ICs in deep submicron CMOS and BiCMOS process have been successively demonstrated. With the aim at accelerating the cost-down of optical communication devices, this thesis explores circuit techniques for optical transceiver design in Si-based IC technologies. The objective goals of this research are to realize 2.5Gbps optical transceiver ICs.
At the transmitter side, a 2V and 2.5Gbps CMOS data serializer has been proposed. High speed parallel to serial data conversion is achieved by means of time-division multiplexer toggled by a low jitter and 8-phases PLL. The maximum conversion rate is in excess of 312.5Mbyte/sec. Moreover, a laser diode driver in the succeeding stage has been implemented to drive an external laser diode. Fabricated in a 0.8mm BiCMOS process; the driver circuit delivers a modulation current of 30mA, a biased current of 10mA and is capable of operating at 3Gbps. The measured eye diagram meets the transition mask required by OC-48.
The front-end ICs at the receiver side developed in this work include a transimpedance amplifier (TIA) and a limiting amplifier (LA), which are implemented in 0.35mm CMOS technology and operated under a 3V supply. The TIA provides a conversion gain of 54dBW with a —3dB bandwidth of 2.5GHz. The limiting amplifier achieves an input sensitivity of 4mv, -3dB bandwidth of 2.2GHz and conversion gain of 40dB. In addition, an oversampling by three data recovery circuits architecture has been proposed.
All the circuit blocks described in this thesis have been thoroughly investigated and measured. The promising performances demonstrated strong potentials for future SoC solutions of optical transceivers in CMOS technology.

關鍵字(中)

★ 傳送器
★ 光纖
★ 接收器
★ 收發機
★ 相位鎖相迴路
★ 資料回覆器

關鍵字(英)

★ Data Recovery
★ Optical
★ Phase-Locked Loop
★ Receiver
★ Transceiver
★ Transmitter

論文目次

Abstracti
Contentiii
List of Figuresvi
List of Tablesix
Chapter 1Introduction1
1.1Motivation1
1.2Thesis Organization2
Chapter 2Phase-Locked Loop5
2.1Introduction5
2.2PLL Architecture6
2.2.1PLL Linear Model7
2.2.2Z-domain Stability8
2.3Building Blocks of the PLL10
2.3.1Phase Frequency Detector10
2.3.2Charge Pump13
2.3.3Loop Filter14
2.3.4Voltage Controlled Oscillator14
2.3.5Divider17
2.4Noise Analysis19
2.5Measurement21
Chapter 3Transmitter24
3.1Introduction24
3.2Data Serializer25
3.3Encoder26
3.4Serializer26
3.5Simulation of Serializer28
3.6Laser Diode Driver30
3.6.1Laser Diode30
3.6.2Block of LD Driver33
3.7Measurement of LD36
Chapter 4Front-End Circuits Design39
4.1Introduction39
4.2Front-End Circuits40
4.3Active Inductor41
4.4Transimpedance Amplifier43
4.4.1Low Input Impedance TIA44
4.4.2Gm Enhancement Technique45
4.4.3TIA Implementation47
4.4.4Simulation Results of TIA48
4.5TIA Measurement Results50
4.6Limiting Amplifier52
4.6.1Gain Cells54
4.6.2Offset Cancellation54
4.6.3Gain Stage Optimization55
4.7Measurement of LA58
Chapter 5Data Recovery61
5.1Introduction61
5.2Data Recovery Architecture62
5.2.1PLL-Based Data Recovery62
5.2.2Oversampling-Based Data Recovery63
5.3Building Blocks of Data Recovery64
5.3.1RX-PLL64
5.3.2Oversampled Block65
5.3.3Phase Decision66
5.3.4Data Decision68
5.3.5Preamble Detector69
5.3.6Byte Alignment69
5.3.7First-In First-Out Memory (FIFO)72
5.4Data Recovery Simulation Results73
Chapter 6Conclusion74
Bibliography77

參考文獻

[1]Roland E. Best, “Phase-Locked Loops: Theory, Design, and Applications”, McGraw-Hill Inc., 2nd ed., 1993.
[2]Behzad Razavi, “Monolithic Phase-Locked Loops and Clock Recovery Circuits”, pp. 1-39, IEEE Press, 1996.
[3]F.M. Gardner, “Charge-Pump Phase-Lock Loops”, IEEE Trans. On Commun., vol. COM-28, pp. 1849-1858, Nov. 1980.
[4]J. P. Hein, and J.W. Scott, “z-Domain Model for Discrete-Time PLL’s”, IEEE Trans. Circuits and Systems, vol. 35, pp. 1391-1400, Nov. 1988.
[5]M. Soyuer and R.G. Meyer, “Frequency Limitation of a Conventional Phase-Frequency Detector”, IEEE J. Solid-State Circuits, vol. 25, pp. 1019-1022, Aug. 1990.
[6]H.O. Hohansson, “A Simple Precharged CMOS Phase Frequency Detector”, IEEE J. Solid-State Circuits, vol. 33, pp. 295-299, Feb.1998.
[7]W.H. Lee, J.D. Cho and S.D. Lee, “A High Speed and Low Power Phase-Frequency Detector and Charge-pump”, IEEE Proceedings of the ASP-DAC, pp.269-272, vol. 1, 1999.
[8]S.O. Jeon, T. S. Cheung and W. Y. Choi, “Phase/Frequency Detectors for high-speed PLL applications”, IEEE Electronics Letters, vol. 34, pp.2120-2121, Oct. 1998.
[9]J.G. Maneatis and M. A. Horowitz, “ Precise Delay Generation Using Coupled Oscillators,” IEEE J. Solid-State Circuits, vol. 28, pp. 1273-1282, Dec. 1993.
[10]J.G. Manteatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE J. Solid-State Circuits, vol. 31, pp. 1723-1732, Nov. 1993.
[11]I. Young, et al., “A 10-110MHz Phase-Locked Loop for Microprocessors,” IEEE International Solid-State Circuits Conference, pp. 50-51, Feb. 1992.
[12]D.G. Wilson, W. Rhee, and B.S. Song, “Integrated RF Receiver Front Ends and Frequency Synthesizers for Wireless,” Tutorial Sec.4.2, IEEE ISCAS, 1996.
[13]T.C. Weigandt, B. Kim and P.R. Gray, “Analysis of Timing Jitter in CMOS Ring Oscillators,” IEEE ISCAS, vol. 4, pp.27-30, 1994.
[14]B. Razavi, “A Study of Phase Noise in CMOS Oscillators,” IEEE J. Solid-State Circuits, pp. 331-343, vol. 31, March 1996.
[15]J. McNeill, “Jitter Ring Oscillators,” IEEE J. Solid-State Circuits, vol. 32, pp. 870-879, June 1997.
[16]F. Herzel and B. Razavi, “A Study of Oscillator Jitter Due to Supply and substrate Noise,” IEEE Transactions on Circuits and Systems, vol. 46, pp. 56-62, Jan. 1999.
[17]J.F. Ewen et al., “Single-chip 1062 Mbaud CMOS transceiver for serial data communication,” IEEE International Solid-State Circuits Conference, pp. 32-33, 1995.
[18]M. Fukaishi et al., “A 4.25 Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture,” IEEE J. Solid-State Circuits, vol. 33, pp. 2139-2147, Dec. 1998.
[19]S. Kim et al., “A 960Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL”, IEEE J. Solid-State Circuits, vol. 32, pp. 691-700, May 1997.
[20]A.X. Widmer and P.A. Franaszek, “A DC-balanced, partitioned-block, 8B/10B transmission code,” IBM J. Res. Develop., vol. 27, pp. 440-451, Sept. 1983.
[21]“1A448 Product Information”, MITEL Semiconductor Ltd. Inc.
[22]J. Tatum and J. Guenter, “Modulating VCSELs: Application Sheet”, Honeywell Inc., MIRCRO SWITCH Division, Feb. 1998.
[23]J. Tatum, D. Smith, J. Guenter and R. Johnson, “High Speed Characteristics of VCSELs”, Honeywell Inc., MICRO SWITCH Division.
[24]D. Johns and K. Martin, “Analog Integrated Circuit Design,” published by John Wiley&Sons Inc., New York, 1996.
[25]K.R. Shastri, K.N. Wong, and K.A. Yanushefski, “1.7 G/s NMOS Laser Driver”, IEEE Custom Integrated Circuits Conference, pp. 5.1.1-5.1.4, 1988.
[26]K.R. Shastri, K.A. Yanushefski, J.L. Hokanson and M.J. Yanushefski, “4.0 Gb/s NMOS Laser Driver”, IEEE Custom Integrated Circuits Conference, pp. 14.7.1-14.7.3, 1989.
[27]M. Banu et al., “10 Gbit/s Bipolar Laser Driver”, IEEE Electronics Letters, vol. 27, pp. 278-280, Jan. 1991.
[28]S. Baumgartner et al., “An Integrated 1.25 Gbit/s Laser Driver/Post Amplifier IC”, IEEE Custom Integrated Circuits Conference, pp. 17-20, 1997.
[29]S.S. Mohan, M. Hershenson, S.P. Boyd, and T.H. Lee, “Bandwidth Extension in CMOS with Optimized On-Chip Inductors,” IEEE J. Solid-State Circuits, vol. 35, pp. 346-355, March 2000.
[30]J.J. Morikuni and S.M. Kang, “An Analysis of Inductive Peaking in Photoreceiver Design,” IEEE J. Solid-State Circuits, vol. 10, pp. 1426-1437, Oct. 1992.
[31]E. Sackinger and W.C. Fischer, “A 3GHz 32dB CMOS Limiting Amplifier for SONET OC-48 Receivers,” IEEE International Solid-State Circuits Conference, pp. 158-159, 2000.
[32]T. Masuda et al., “45GHz Transimpedance 32dB Limiting Amplifier and 40Gbps 1:4 High-Sensitivity Demultiplexer with Decision Circuit using SiGe HBTs for 40Gbps Optical Receiver,” IEEE International Solid-State Circuits Con., pp. 60-61, 2000.
[33]F.T. Chien and Y.J. Chan, “Bandwidth Enhancement of Transimpedance Amplifier by a Capacitive-Peaking Design,” IEEE J. Solid-State Circuits, vol. 34, pp. 1167-1170, Aug. 1999.
[34]S.B. Baker and C. Thoumazou, “Low Noise CMOS Common Gate Optical Preamplifier Using Active Feedback,” IEEE Electronic Lett., vol. 34, pp. 2235-2237, Nov. 1998.
[35]R. Reimann and H.M. Rein, “Bipolar High-Gain Limiting Amplifier IC for Optical Fiber Receivers Operating Up to 4Gbit/s,” IEEE J. Solid-State Circuits, vol. 22, pp. 504-511, Aug. 1987.
[36]Y.M. Greshishchev and P. Schvan, “A 60-dB Gain, 55-dB Dynamic Range, 10-Gb/s Broad-Band SiGe HBT Limiting Amplifier,” IEEE J. Solid-State Circuits, vol. 34, pp. 1914-1920, Dec. 1999.
[37]E. Sackinger and W.C. Fischer, “A 3GHz, 32dB CMOS Limiting Amplifier for SONET OC-48 Receivers,” IEEE International Solid-State Circuits Con., pp. 158-159, 2000.
[38]M. Soda et al., “A Si Bipolar Chip Set for 10Gb/s Optical Receiver,” IEEE International Solid-State Circuits Con., pp. 100-101, 1992.
[39]J. Hauptmann et al., “A Low-Noise Amplifier with Automatic Gain Control and Anticlipping Control in CMOS Technology,” IEEE J. Solid-State Circuits, vol. 27, pp. 974-981, Dec. 1992.
[40]M. Rau et al., ”Clock/Data Recovery PLL Using Half-Frequency Clock,“ IEEE J. Solid-State Circuits, vol. 32, pp. 1156-1159, July 1997.
[41]M. Soda et al., “A 2.4-Gb/s CMOS Clock Recovering 1:8 Demultiplexer,” IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp. 69-70, 1997.
[42]John F. Ewen et al., “Single-Chip 1062Mbaud CMOS Transceiver for Serial Data Communication,” IEEE International Solid-State Circuits Con., pp. 32-33, 1995.
[43]B. Lai, R.C. Walker, “A Monolithic 622Mb/s CMOS Extraction Data Retiming Circuit,” IEEE International Solid-State Circuits Con., pp. 144-145, 1991.
[44]K. Kishine et al., “A 2.5-Gb/s Clock and Data Recovery IC with Tunable Jitter Characteristics for Use in LAD’s and WAN’s,” IEEE J. Solid-State Circuits, vol. 34, pp. 805-812, June 1999.
[45]M. Fukaishi et al., “A 20Gb/s CMOS Multi-Channel Transmitter and Receiver Chip Set for Ultra-High Resolution Digital Display,” IEEE International Solid-State Circuits Con., pp. 260-261, 2000.
[46]T. Ellermeyer et al., “A 10Gb/s Eye Opening Monitor IC for Decision-Guided Optimization of the Frequency Response of an Optical Receiver,” IEEE International Solid-State Circuits Con., pp. 50-51, 2000.
[47]R.G. James et al., “A 0.5-3.5Gb/s Low-Power Low-Jitter Serial Data CMOS Transceiver,” IEEE International Solid-State Circuits Con., pp. 352-353, 1999.
[48]C.K. Yang et al., “A 0.5-um CMOS 4.0-Gbit/s Serial Link Transceiver with Data Recovery Using Oversampling,” IEEE J. Solid-State Circuits, vol. 33, pp. 713-722, May 1998.
[49]C.K. Yang and M.A. Horowitz, “A 0.8-um CMOS 2.5 Gb/s Overampling Receiver and Transmitter for Serial Links,” IEEE J. Solid-State Circuits, vol. 31, pp. 2015-2023, Dec. 1996.
[50]K. Lee et al., “`1.04 GBd Low EMI Digital Video Interface System Using Small Swing Serial Link Techique,” IEEE J. Solid-State Circuits, vol. 33, pp. 816-823, May 1998.
[51]A. Fiedler, R. Mactaggart, J. Welch and Krishnan, “A 1.0625Gbps Transceiver with 2x-Oversampling and Transmit Signal Pre-Emphasis,” IEEE International Solid-State Circuits Con., pp. 238-239, 1997.
[52]S. Kim et al., ”A 960-Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL,” IEEE J. Solid-State Circuits, vol. 32, pp. 691-700, May 1997.

指導教授

陳巍仁(Wei-Zen Chen)

審核日期

2001-6-19

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