A 2.5V,0.35um,2.5Gbps 傳送接收器設計

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張紹銘(Shao-Ming Chang ) 查詢紙本館藏

畢業系所

電機工程研究所

論文名稱

A 2.5V,0.35um,2.5Gbps 傳送接收器設計
(A 2.5V, 0.35um, 2.5Gbps transceiver design)

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摘要(中)

當晶片和外界通訊時，輸入/輸出裝置是決定晶片間是否成功傳送接收的重要因素。由於製程技術的縮小使得VLSI的操作頻率和電路複雜度增加，在高速連接上串音(crosstalk)、反射(reflection)、時脈偏斜(clock skew)、接地反彈(ground bounce)現象變成非常重要的，這些現象將使得電路設計時無法符合輸入/輸出裝置要求。
在本論文中有兩個主要要旨，第一，我們將焦點集中於在高速連接上信號完整(signal integrity)的概念和輸入/輸出電路的設計。其次，基於信號完整性和寄生效應(parasitics)為考量，我們將提出一個使用低電壓振幅和差動信號的傳送器和接收器。
傳送器和接收器以TSMC 0.35μm 1P4M CMOS製程來實現，傳送器和接收器之間資料傳輸速率是2.5G bits/sec而且微細長片線(micro-strip line)的傳輸長度是0.5m，直流電源2.5V和1.3V提供這個裝置。

摘要(英)

When a chip communicates with external world, I/O device is the key component to successfully transmit and receive data between chips. As operating frequency and circuit complexity of VLSI is increased due to process technologies scale-down . Crosstalk, reflection, clock skew, ground bounce become very critical in the high-speed link. These effects will prevent design from fitting the requirement of I/O device.
There are two major topics in this thesis. First, we should focus on the overview of signal integrity and design of I/O circuit in the high-speed link. Secondly, base on consideration of signal integrity and parasitics. We will propose the transmitter and receiver that use low voltage swing and differential signalling.
Transmitter and receiver are implemented by TSMC 0.35μm 1P4M CMOS technologies. The data transfer rate is 2.5G bits/sec and length of micro-strip line is 0.5m between transmitter and receiver. DC 2.5V and 1.3V supplies the device.

關鍵字(中)

★ 低電壓振幅
★ 信號完整
★ 傳送接收器
★ 差動信號
★ 高速

關鍵字(英)

★ High-Speed
★ signal integrity
★ transceiver

論文目次

1. Introduction……………………………………………………………… 1
1.1 Motivations………………………………………………………………1
1.2 Overview of signal integrity in the high-speed circuits………………… 2
Why analysis signal integrity…………………………………………… 2
Crosstalk ……………………………………………………………… 2
Relfection……………………………………………………………… 5
Ground bounce………………………………………………………… 7
1.3 Driver design methodology…………………………………………… 10
Driver Overview……………………………………………………… 10
Single-ended open drain driver……………………………………… 11
Single-ended Trans-Impedance Amplifier (TIA)……………………… 12
Differential open drain driver………………………………………… 13
Differential current steering driver…………………………………… 14
1.4 The design consideration for the high-speed circuit………………… 16
Termination technique…………………………………………………16
Low-voltage swing…………………………………………………… 17
Single-ended and differential transmission…………………………… 18
1.5 Thesis organization……………………………………………………18
2. Architecture Overview………………………………………………… 20
2.1 Introduction……………………………………………………………20
2.2 Clock generator and 2 Dimension Array Delay Locked Loop (2-D DLL)…………………………………………………………………………22
2.3 Transmitter…………………………………………………………… 22
Data splitter…………………………………………………………… 23
Preamplifier……………………………………………………………24
Driver…………………………………………………………………24
2.4 Termination…………………………………………………………… 25
2.5 Receicver……………………………………………………………… 25
Front-end amplifier…………………………………………………… 25
Sampler………………………………………………………………… 26
Set-Reset (SR) Latch……………………………………………………26
3. Clock generator and 2-Dimension array DLL………………………27
3.1 Architecture Introduction………………………………………… 27
3.2 Overview of PLL and DLL…….………………………………………30
PLL introduction……………………………………………………30
DLL introduction………………………………………………… 31
3.3 Detail circuit design……………………………………………… 31
Unit differential delay buffer…………………………………31
Bias generator ……………………………………………… 32
Differential-to-Single Circuit…………………………………33
Swing adjuster……….…………………………………………… 34
Phase Frequency Detector (PFD)…………………………………35
Charge Pump………………………………………………………… 36
Frequency divider………………………………………………… 37
3.4 System response and stability…………………………………… 38
3.5 Simulation result…….………………………………………………41
Simulation result of PLL…………………………………………41
Simulation result of DLL…………………………………………44
4. Transmitter………………………………………………………………47
4.1 Data Splitter………………………………………………………… 47
4.2 Pre-amplifier………………………………………………………… 50
4.3 Driver……………………………………………………………………51
4.4 Simulation Result…………………………………………………… 53
5. Receiver….………………………………………………………………56
5.1 Front-end amplifier………………………………………………… 56
5.2 Sampler………………………………………………………………… 57
5.3 S-R latch……………………………………………………………… 58
5.4 Simulation result…………………………………………………… 59
6. Conclusion……………………………………………………………… 61
7. Reference…………………………………………………………………62

參考文獻

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指導教授

蘇朝琴(Chauchin Su)

審核日期

2001-7-12

推文