前瞻音訊解碼系統的軟硬體核心技術開發及設計

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姓名

劉俊男(Chun-Nan Liu) 查詢紙本館藏

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電機工程學系

論文名稱

前瞻音訊解碼系統的軟硬體核心技術開發及設計
(Design of Hardware and Software Key Techniques for Advanced Audio Decoder System)

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摘要(中)

數位音訊編碼已經非常流行而且被廣泛的應用在各種不同的領域中，傳統的數位音訊解碼器實現大致上可以分為三種類型，包括硬體實現、軟體實現及軟體硬體共同設計，在本論文中會針對這三種方法的關鍵技術提出相對應的解決方案，並分成四個研究的主題。在第一個主題中，我們提出一個純硬體的設計來實現一個低功率的先進式數位音訊(AAC)解碼器，根據解碼演算法的特性，整個系統會被切分為四個主要的運算模組，然後在低功率跟低複雜度的考量下，我們從架構的層級以及演算法的層級對個別的模組和整合的系統都提出最佳化的方法。在低成本的考量下，雙聲道的數位音訊處理也只需要單一套的硬體即可有效率的處理，在UMC 0.18 um 1P6M的製程下，我們所設計的AAC解碼器只需要3 MHz就可以達到即時播放的要求，而且如果在44.1 KHz的音樂取樣頻率條件下其功率消耗更是只需要2.45 mW。
　　第二主題部分則是針對單一解碼器支援多種音訊標準的設計進行探討，主要的動機在於目前並沒有一個統一的音訊標準可以取代其他的標準，因此在單一的產品中必須具備支援多標準的能力才能符合消費者的需求，在此論文中我們提出一個Configurable Common Filterbank Processor (CCFP)的處理單元，它可以用來作為一般通用處理器的加速器來提升系統的效能，此設計也是採用UMC 0.18 um 的製程，所需要的gate counts只有26.7 Kgates，而所需的操作頻率只需在1.3 MHz到3.6 MHz的範圍內，對AC-3、MP3及AAC三個標準其功率消耗則分別是0.9 mW、3.2 mW以及1 mW。
　　第三個主題部分則是針對軟硬體共同設計做介紹，因為在一個SoC的平台上可以同時提供通用處理器所具備的高彈性優點以及客製化硬體的高效能、低功率消耗特性，所以我們特別提出軟硬體共同設計的方式來實現數位音訊的解碼。首先，我們提出一個分析的模型，藉由此模型分析的結果可以將系統做最合適的軟體及硬體切分，然後便可針對硬體及軟體進行個別的最佳化設計，經由軟硬體共同設計搭配在第二個主題所設計的硬體加速器(CCFP)，我們的系統可以比單獨軟體在ARM上執行的效能再提升約15倍左右。
　　最後一個主題的部份則是數位音訊在DSP上的實現，以DSP的實現方式可以達到比較高的彈性，可以較容易增加一些新的功能，但是由於目前比較高效能的DSP都是採用VLIW的架構，表示其可以在一個運算週期內同時執行多道的運算指令，然而傳統的數位音訊演算法還都是循序執行的方式，如果要在以VLIW架構的DSP上得到較高的效能就必須將演算法改寫成可以平行處理的方式，本論文的部份則是以AAC為實例來探討各種在VLIW架構DSP上的最佳化方式，我們最後所實現的AAC解碼器只需操作在15 MHz就可以達到即時播放的要求，而所使用的程式記憶體及資料記憶體則是各要27 Kbytes。

摘要(英)

Digital audio coding is popular and has been applied in many areas. The conventional implementation approaches for these audio decoders can be categorized to three methods, i.e. dedicated hardware, software-based general purpose processor (GPP) and hardware/software co-design. This dissertation covers the key techniques of all these methods and brings four contributions. First, an implementation of low power and pure hardware AAC audio decoder system is presented. Based on the characteristics of each decoding block, the AAC system is partitioned into four separate modules. For the low power and low complexity considerations, architectural and algorithmic level approaches are adopted in both the individual modules and the whole system. Referring to stereo processing, a single hardware is shared for the channel pairs with the low cost consideration. The hardware operations of each module are well scheduled with high utilization of pipeline, and further the parallel processing among blocks are joined to increase the efficiency. A 48 % power savings can be reached by using the pipeline and parallel techniques of the channel pair. The proposed AAC decoder is realized in UMC 0.18 ?m 1P6M technology and operated at only 3 MHz in the worst case. The power dissipation is only 2.45 mW at the sampling frequency of 44.1KHz.
Second, due to audio applications for mobile phone and portable devices are increasingly popular. To attract consumer interest, a multi-standard design on a single device is the requirement of current audio decoder development. We present a configurable common filterbank processor (CCFP) for AC-3, MP3 and AAC audio decoder. It is used as an accelerator for general purpose processors to improve performance. All the filterbank transforms are derived to even- or odd-point IFFT flows. In the architecture, a fully pipelined approach is developed which can be configured for different operation modes. This design is synthesized using UMC 0.18 µm library and takes about 26.7K gates. It can be executed at a very low operation frequency with the range of 1.3 to 3.6 MHz. Besides, the power consumption is only 0.9 mW, 3.2 mW and 1 mW for AC-3, MP3 and AAC respectively.
Third, SoC integration platform provides the flexibility of general-purpose processors and the high performance and low power consumption of custom hardware. We present a Hardware/Software co-design method for the implementation of AAC audio decoder. This approach not only considers the characteristics of algorithms, but also provides the numerical decision for evaluation of the various approaches. The overall system is first analyzed and profiled with ARM profiler. Then the decoder system is partitioned into software part and hardware part respectively based on the property of analysis. Besides, a multi-standard audio decoder based on the SoC Hardware/Software co-design approach is also presented. It supports popular audio formats including AC-3, MP3 and AAC. By using the accelerator and the processor with cache enabled, the overall system can get more than 15x speedup compared to software-based ARM audio decoder.
Finally, we propose VLIW-aware software optimization techniques for the AAC decoding blocks on the parallel architecture core DSP (PACDSP) processor. This approach provides the flexibility for adding new extensions and solves two important issues, low power consumption and limited resources problems on DSP for portable devices. We change the traditional sequential algorithms into parallel processes and minimize the memory utilization of each block. The realized decoder can be operated at a lower frequency of only 15 MHz and needs only 27 Kbytes of program memory and 27 Kbytes of data memory.

關鍵字(中)

★ 硬體架構設計
★ 低功率
★ 解碼器
★ 系統單晶片
★ 軟體設計
★ 數位音訊處理

關鍵字(英)

★ Decoder
★ Low Power
★ Hardware Architecture Design
★ Digital Signal Processing
★ SoC
★ Software Design

論文目次

1. Introduction 1
1.1 MOTIVATION 1
1.2 OVERVIEW OF ADVANCED AUDIO CODING STANDARDS 3
1.3 THE ORGANIZATION OF THE DISSERTATION 5
2 Low Power System Design for MPEG-2/4 Audio Decoder Using Pure ASIC Approach 6
2.1 OVERVIEW OF AAC DECODING FLOW 6
2.2 DESIGN CONSIDERATIONS 9
2.3 PARALLEL PLA BASED CODEWORD DECODER (PPCD) 13
2.4 REDUCED LOOKUP TABLE INVERSE QUANTIZER (RLIQ) 19
2.5 HARDWARE SHARED SIGNAL PROCESSOR (HSSP) 21
2.6 FULLY PIPELINED FILTERBANK (FPF) 24
2.7 LOW POWER SYSTEM INTEGRATION AND SCHEDULING 28
2.8 IMPLEMENTATION RESULTS 30
3 A Configurable Common Filterbank Processor for Multi-Standard Audio Decoder 35
3.1 MOTIVATION 35
3.2 OVERVIEW OF FILTERBANK 36
3.3 FAST ALGORITHMS FOR FILTERBANK 39
3.4 ARCHITECTURE DESIGN OF CONFIGURABLE COMMON FILTERBANK PROCESSOR 41
3.4.1 Design consideration and derivation 41
3.4.2 Configurable and Fully Pipelined Architecture Design 43
3.4.3 Memory Consideration and Access Scheme 46
3.5 IMPLEMENTATION RESULTS 49
4 Hardware/Software Co-Design of Audio Decoder System 57
4.1 MOTIVATION 57
4.2 A HARDWARE/SOFTWARE CO-DESIGN CASE STUDY ON MPEG AAC AUDIO DECODER 58
4.2.1 Hardware/Software Co-Design Methodology 58
4.2.2 Hardware/Software Partition 60
4.2.3 System Architecture Design and Implementation 64
4.2.4 The Modified Regressive Approach 66
4.2.5 Implementation Results 69
4.3 MULTI-STANDARD AUDIO DECODER WITH PLATFORM BASED SOC HARDWARE/SOFTWARE CO-DESIGN APPROACH 73
4.3.1 Platform Based SoC Hardware/Software Co-Design Methodology 73
4.3.2 Hardware and Software Design 74
4.3.3 Implementation Results 76
5 VLIW-Aware Software Optimization of AAC Decoder on Parallel Architecture Core DSP (PACDSP) Processor 78
5.1 MOTIVATION 78
5.2 INTRODUCTION OF VLIW-BASED PACDSP 79
5.3 A LOW-LATENCY MULTI-LAYER PREFIX GROUPING TECHNIQUE FOR PARALLEL HUFFMAN DECODING OF MULTIMEDIA STANDARDS 81
5.3.1 Overview of Previous Works 81
5.3.2 Proposed Multi-layer Prefix Grouping Technique 84
5.3.3 Two-level Table Lookup for Multi-layer Prefix Grouping 88
5.3.4 Parallel Processing between Two-level Table Lookup and Direct Table Lookup 90
5.3.5 Optimizations for AAC Huffman Decoding 91
5.4 MEMORY EFFICIENT REALIZATION OF IQ AND RESCALE 101
5.5 LOOP SHARING OF STEREO PROCESSING 102
5.6 VLIW PARALLEL PROCESSING OF FILTERBANK 104
5.7 IMPLEMENTATION RESULTS 104
6 Conclusions 107
6.1 SUMMARY OF CONTRIBUTIONS 107
6.2 FUTURE WORK 109
References 110
Publication List 116

參考文獻

[1] Advanced Television Systems Committee Standard Doc. A/52A, “Digital audio compression standard (AC-3),” Aug. 2001.
[2] ISO/IEC 11172-3, “Information technology-coding of moving pictures and associated audio for digital storage media at up to 1.5 Mbits/s. Part3: Audio,” Nov. 1991.
[3] ISO/IEC JTC1/SC29/WG11 No.1650, “ISO 13818-7 (MPEG-2 Advanced Audio Coding, AAC),” Apr. 1997.
[4] ISO/IEC FCD 14496-3, “Information technology-very low bitrate audio-visual coding Part 3: Audio,” May 1998.
[5] ISO/IEC 14496-3:2001/Amd 1:2003, “Bandwidth extension”.
[6] ISO/IEC 14496-3:2001/Amd 2:2004, “Parametric coding for high quality audio”.
[7] M. A. Watson and P. Buettner, “Design and implementation of AAC decoders,” IEEE Trans. Consumer Electronics, vol. 46, issue 3, pp.819-824, Aug. 2000.
[8] J. Chen and H. M. Tai, “MPEG-2 AAC decoder on a fixed-point DSP,” IEEE Trans. Consumer Electronics, vol. 45, issue 4, pp.1200-1205, Nov. 1999.
[9] V. Mesarovic, N. D. Hemkumr and M. Dokic, “MPEG-4 AAC audio decoding on a 24-bit fixed-point dual-DSP architecture,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol. 3, pp.706-709, May 2000.
[10] K. H. Bang, J. S. Kim, N. H. Jeong, Y. C. Park and D. H. Youn, “Design optimization of MPEG-2 AAC decoder,” IEEE Trans. Consumer Electronics, vol. 47, issue 4, pp.895-903, Nov. 2001.
[11] K. S. Lee, Y. C. Park and D. H. Youn, “Software optimization of the MPEG-audio decoder using a 32-bit MCU RISC processor,” IEEE Trans. Consumer Electronics, vol. 48, issue 3, pp.671-676, Aug. 2002.
[12] Y. Takamizawa, K. Nadehara, M. Boegli, M. Ikekawa and I. Kuroda, “MPEG-2 AAC 5.1-channel decoder software for a low-power embedded RISC microprocessor,” in Proc. IEEE Workshop on Signal Processing Systems (SIPS), pp.351-360, Oct. 1999.
[13] P. Liu, L. Liu, N. Deng, X. Fu, J. Liu, Q. Liu, Guocheng Zhang and Bin He, “VLSI implementation for portable application oriented MPEG-4 audio codec,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), pp.777-780, May 2007.
[14] H. Zhang, M. Lu and G. Wang, “An ASIC implementation of MPEG audio decoders,” in Proc. 7th Int. Conf. ASIC, pp.754-757, Oct. 2007.
[15] D Zhou, P. Liu, J. Kong, Y. Zhang, B. He and N. Deng, “An SoC based HW/SW co-design architecture for multi-standard audio decoding,” in Proc. IEEE Asian Solid-State Circuits Conference (ASSCC), pp.200-203, Nov. 2007.
[16] S. R. Quackenbush and Y. Toguri, “Revised report on complexity of MPEG-2 AAC tools,” ISO/IEC JTC1/SC29/WG11 N2005, Feb. 1998.
[17] P. C. Wang, Y. R. Yang, C.-L. Lee and H. Y. Chang, “A memory-efficient Huffman decoding algorithm,” in Proc. Int. Conf. Advanced Information Networking and Applications, vol. 2, pp. 475-479, Mar. 2005.
[18] B. J. Shieh, Y. S. Lee and C. Y. Lee, “A high-throughput memory-based VLC decoder with codeword boundary prediction,” IEEE Trans. Circuits and Systems for Video Technology, vol. 10, issue 8, pp.1514-1521, Dec. 2000.
[19] R. Hashemian, “Design and hardware implementation of a memory efficient Huffman decoding,” IEEE Trans. Consumer Electronics, vol. 40, issue 3, pp.345-352, Aug. 1994.
[20] S. M. Lei and M. T. Sun, “An entropy coding system for digital HDTV applications,” IEEE Trans. Circuits and Systems for Video Technology, vol. 1, issue 1, pp.147-155, Mar. 1991.
[21] K. S. Lee, N. H. Jeong, K. H. Bang and D. H. Youn, “A VLSI implementation of MPEG-2 AAC decoder system,” in Proc. 1st IEEE Asia Pacific Conf. ASICs, pp.139-142, Aug. 1999.
[22] T. H. Tsai, W. C. Chen and C. N. Liu “A low power VLSI implementation for variable length decoder in MPEG-1 layer III,” in Proc. IEEE Int. Conf. Multimedia & Expo (ICME), vol. 1, pp.133-136, July 2003.
[23] K. S. Lee, H. O. Oh, Y. C. Park, and D. H. Youn, “High quality MPEG-audio layer III algorithm for a 16-bit DSP,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol. 2, pp.205-208, May 2001.
[24] T. H. Tsai and C. C. Yen, “A high quality re-quantization/quantization method for MP3 and MPEG-4 AAC audio coding,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol. 3, pp.851-854, May 2002.
[25] H. J. Hee, M. H. Sunwoo and J. H. Moon, “Novel non-linear inverse quantization algorithm and its architecture for digital audio codecs,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), pp.357-360, May 2007.
[26] ISO/IEC 13818-4, “Information technology-generic coding of moving picture and associated audio information, Part 4: conformance testing,” Dec. 1998.
[27] P. Duhamel, Y. Mahieux and J. P. Petit, “A fast algorithm for the implementation of filter banks based on `time domain aliasing cancellation',” in Proc. Int. Conf. Acoustics, Speech, and Signal Processing, vol. 3, pp.2209-2212, Apr. 1991.
[28] V. Z. Mesarovic, R. Rao, M. V. Dokic and S. Deo, “Selecting an optimal Huffman decoder for AAC,” AES Conv. Paper 5436, Sep. 2001.
[29] C. W. Ryu, D. H. Lee, H. J. Chi, K. S. Kwan, T. H. Kim and J. S. Park, “Design of digital audio DSP core,” The 1st Int. Forum on Strategic Technology, pp.59-62, Oct. 2006.
[30] Y. Jhung and S. Park, “Architecture of dual mode audio filter for AC-3 and MPEG,” IEEE Trans. Consumer Electronics, vol. 43, issue 3, pp.575-585, Aug. 1997.
[31] W. Lau and A. Chwu, “A common transform engine for MPEG and AC3 audio decoder,” IEEE Trans. Consumer Electronics, vol. 43, issue 3, pp.559-566, Aug. 1997.
[32] W. S. Ko, S. K. Yoo, S. W. Park, J. S. Kim and D. H. Youn, “A VLSI implementation of dual AC-3 and MPEG-2 audio decoder,” IEEE Trans. Consumer Electronics, vol. 44, issue 3, pp.872-877, Aug. 1998.
[33] K. H. Bang, N. H. Jeong, J. S. Kim, Y. C. Park and D. H. Youn, “Design and VLSI implementation of a digital audio-specific DSP core for MP3/AAC,” IEEE Trans. Consumer Electronics, vol. 48, issue 3, pp.790-795, Aug. 2002.
[34] T. H. Tsai, Y. C. Yang and C. N. Liu “A hardware/software co-design of MP3 audio decoder,” Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol. 41, pp.111-127, Aug. 2005.
[35] M. H. Cheng and Y. H. Hsu, “Fast IMDCT and MDCT algorithms-a matrix approach,” IEEE Trans. Signal Processing, vol. 51, issue 1, pp.221-229, Jan. 2003.
[36] S. W. Lee, “Improved algorithm for efficient computation of the forward and backward MDCT in MPEG audio coder,” IEEE Trans. Circuits and Systems II: Express Briefs, vol. 48, issue 10, pp.990-994, Oct. 2001.
[37] C. H. Chen, B. D. Liu and J. F. Yang, “Recursive architectures for realizing modified discrete cosine transform and its inverse,” IEEE Trans. Circuits and Systems II: Express Briefs, vol. 50, issue 1, pp.38-45, Jan. 2003.
[38] N. Vladimir and F. Gerhard, “Computation of forward and inverse MDCT using Clenshaw's recurrence formula,” IEEE Trans. Signal Processing, vol. 51, issue 5, pp.1439-1444, May 2003.
[39] J. Takala, J. Rostrom, T. Vaaraniemi, H. Herranen and P. Ojala, “A low-power MPEG audio layer III decoder IC with an integrated digital-to-analog converter,” IEEE Trans. Consumer Electronics, vol. 46, issue 3, pp.896-902, Aug. 2000.
[40] S. J. Nam, B. H. Kim, C. D. Im, J. B. Kim, S. J. Lee, S. S. Jeong, J. K. Kim and S. J. Park, “A low power MPEG I/II layer 3 audio decoder,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol. 2, pp.353-356, May 2001.
[41] ARM AudioDE, http://www.arm.com/products/DataEngines/audioDE.html.
[42] Performance characteristics of ARM7TDMI, http://www.arm.com/products/CPUs/ ARM7TDMI.html.
[43] K. Castille, “TMS320C62x/C67x power consumption summary (Rev. C),” TI application report, July 2002.
[44] ARM website, http://www.arm.com.
[45] S. Chandramouli and G. Maheshwaramurthy, “Implementation of AC-3 decoder on TMS320C62x,” TI application report, Jan. 2001.
[46] T. H. Tsai, C. N. Liu and Y. W. Wang, “A pure-ASIC design approach for MPEG-2 AAC audio decoder,” in Proc. 4th IEEE Int. Conf. Information, Communications & Signal Processing and 4th Pacific-Rim Conf. Multimedia (ICICS-PCM), vol. 3, pp.1633-1636, Dec. 2003.
[47] ARM MPEG-4 AAC LC decoder technical specification, June 2003.
[48] ATEME, “Audio encoder and decoder for DSP,” http://www.ateme.com, 2003.
[49] Audio compression algorithm implementations: clock rate and memory requirements, http://www.bdti.com/articles/ACAI_table.html.
[50] SPIRIT DSP, “MP3 decoder,” http://www.spiritdsp.com, 2006.
[51] ARM, Integrator/AP User Guide, Apr. 2001.
[52] H. C. Chiang and J. C. Liu, “Regressive implementations for the forward and inverse MDCT in MPEG audio coding,” IEEE Signal Processing Letters, vol. 3, no. 4, Apr. 1996.
[53] T. H. Tsai and C. N. Liu, “Architecture design for MPEG-2 AAC filterbank decoder using modified regressive method,” in Proc. IEEE Int. Conf. Acoustics, Speech, and Signal Processing (ICASSP), vol. 3, pp. 3216-3219, May 2002.
[54] Texas Instruments, “TMS320C6000 technical brief,” Feb. 1999.
[55] Philips Electronics, “Trimedia, TM1300 preliminary data book,” Oct. 1999, first draft.
[56] Analog Devices, “TigerSHARC embedded processor,” Dec. 2006.
[57] David C. W. Chang, I. T. Liao, J. K. Lee, W. F. Chen, S. Y. Tseng and C. W. Jen, “PAC DSP core and application processors,” in Proc. IEEE Int. Conf. Multimedia and Expo, pp. 289-292, July 2006.
[58] David C. W. Chang, I. T. Liao, S. Y. Tseng and C. W. Jen, “PAC DSP core and its applications,” in Proc. IEEE Asian Solid-State Circuits Conference, pp. 19-22, Nov. 2006.
[59] ISO/IEC 10918-1, “Digital comprssion and coding of continuous-tone still images: requirements and guidelines,” 1993.
[60] ISO/IEC 13818-2, “Information technology-generic coding of moving pictures and associated audio, Part 2: Video,” 1995.
[61] ISO/IEC 14496-2, “Information technology-coding of audio visual objects, Part 2: Visual,” 2001.
[62] ITU-T H.264, “Advanced video coding for generic audiovisual services,” 2005.
[63] C. T. Hsieh and S. P. Kim, “A concurrent memory-efficient VLC decoder for MPEG applications,” IEEE Trans. Consumer Electronics, vol. 42, issue 3, pp. 439-446, Aug. 1996.
[64] C. D. Chien, K. P. Lu, Y. M. Chen, J. I. Guo, Y. S. Chu and C. L. Su, “An area-efficient variable length decoder IP core design for MPEG-1/2/4 video coding applications,” IEEE Trans. Circuits and Systems for Video Technology, vol. 16, issue 9, pp. 1172-1178, Sep. 2006.
[65] B. Sheng, W. Gao, D. Xie and D. Wu, “An efficient VLSI architecture of VLD for AVS HDTV decoder, ” IEEE Trans. Consumer Electronics, vol. 52, issue 2, pp, 696-701, May 2006.
[66] J. Nikara, S. Vassiliadis, J. Takala and P. Liuha, “Multiple-symbol parallel decoding for variable length codes,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 12, issue 7, pp. 676-685, July 2004.
[67] J. S. Lee, J. H. Jeong and T. G. Chang, “An efficient method of Huffman decoding for MPEG-2 AAC and its performance analysis,” IEEE Trans. Speech and Audio Processing, vol. 13, no. 6, pp. 1206-1209, Nov. 2005.
[68] J. H. Jiang, C. C. Chang and T. S. Chen, “An efficient Huffman decoding method based on pattern partition and look-up table,” in Proc. Fifth Asia-Pacific Conf. Communications and Fourth Optoelectronics and Communications Conference, vol. 2, pp. 904-907, Oct. 1999.
[69] S. Tao, S. Mudar and Z. Jingli, “Memory efficient and low complexity variable length decoding for MPEG-4 applications,” in Proc. Int. Conf. Parallel Processing Workshops (ICPPW 2007), pp. 38-43, Sep. 2007.
[70] S. Quackenbush and J. Herre, "MPEG surround," IEEE Multimedia, vol. 12, issue 4, pp.18-23, Oct. 2005.
[71] J. Breebaart, “Analysis and synthesis of binaural parameters for efficient 3D audio rendering in MPEG Surround”, in Proc. IEEE Int. Conf. Multimedia & Expo (ICME), July 2007.
[72] Tensilica white paper, “Low-power, low-overhead, high-fidelity digital sound for SoCs: Tensilican’s HiFi 2 audio engine,” May 2007.

指導教授

蔡宗漢(Tsung-Han Tsai)

審核日期

2008-6-13

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