應用於多兆元網速乙太網路接收機 類比迴音消除器之最小均方演算法電路設計

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姓名

林新評(Hsin-Ping Lin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於多兆元網速乙太網路接收機類比迴音消除器之最小均方演算法電路設計
(A Design of Least Mean Square Algorithm Circuit for Analog Echo Canceller of Multi-Gbps Ethernet Receiver)

相關論文

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摘要(中)

隨著現今科技的發展和普及，人們對網路的依賴性也愈來愈高，且對裝置或設備的傳輸速度需求也日漸提高，而在高速乙太網路傳輸系統中，如2.5GBASE-T或 5GBASE-T系統，消除迴音干擾是一個重要議題。傳統的迴音消除器常以數位電路實現，而迴音通道響應可以分成若干段，其最大值落於最前段，若在此數位迴音消除器中加入類比迴音消除器，則可以將此最大值在進入數位電路前先行消除，達成減少後續數位電路位元數的效果，而此類比迴音消除器中，需要一個類比演算法電路來提供類比濾波器之係數。
本論文根據IEEE 802.3bz™-2016 規範標準，實現一類比最小均方演算法電路，並且主要分為乘法器電路與積分器電路兩個部分，前者採用吉爾伯特單元(Gilbert cell)作為演算法之乘法器，實現類比輸入之係數和類比輸入之資料相乘功能，並配合系統環境之輸入擺幅，在提高輸入擺幅的同時，也能兼顧線性度方面的表現；後者之架構則為切換式電容(Switched-capacitor)積分器，實現演算法之加法功能與係數儲存之作用，調整乘法器之增益和積分器之回授電容與積分電容的比例，可以決定此演算法電路之步階值(Step size)，並且以全差動電路架構實現之，可以降低製程偏移、電壓偏移與溫度對系統之影響，使電路有較好的誤差表現。
本論文採用TSMC 40nm CMOS標準製程，晶片面積約為0.25mm¬¬2¬(包含I/O PAD)，電源電壓為2.5V和0.9V，操作頻率為200MHz，核心電路功耗約為3.21mW，而整體電路之平均誤差為-47.31dB。

摘要(英)

With the development and popularization of today′s technology, people′s dependence on the network is getting higher, and the demand for transmission speed of devices or equipment is also increasing. In high-speed Ethernet transmission systems, such as 2.5GBASE-T or 5GBASE-T system, eliminating echo interference is an important issue. Traditional echo cancellers are often implemented with digital circuits, and the echo channel response can be divided into several segments, the maximum value of echo channel response falls at the forefront. If an analog echo canceller is added to the traditional digital echo canceller, the maximum value can be eliminated before entering the digital circuit to achieve the effect of reducing the number of bits in the subsequent digital circuit. In this analog echo canceller, an analog algorithm circuit is required to provide the coefficients of the analog filter.
According to the IEEE 802.3bz™-2016 specification standard, this thesis presents a design of an analog Least Mean Square algorithm circuit, which is composed of into two parts: a multiplier circuit and an integrator circuit. The former uses the architecture of Gilbert cell as the multiplier of the algorithm to realize the multiplication function of the analog coefficient input and the analog data input, and adjust the input swing based on the system environment, while improving the input swing, it can also have a good the performance of linearity; the latter uses a switched-capacitor integrator, which realizes the addition function of the algorithm and the function of coefficient storage. Adjusting the gain of the multiplier and the ratio of the feedback capacitor of the integrator to integral capacitor of the integrator can determine the step size of the algorithm circuit, and realize this design with a fully differential architecture can reduce the influence of process deviation, voltage deviation and temperature on the system, so that this design has better performance of error value.
This circuits are designed in TSMC 45 nm CMOS LOGIC General Purpose Superb (40G) ELK Cu 1P10M 0.9/2.5V, the chip area is 0.25mm2 (including I/O PAD), the supply voltage is 2.5V and 0.9V, the operating frequency is 200MHz, and the power consumption of the core circuit is 3.21mW. Finally, the average error of the whole chip is -47.31dB.

關鍵字(中)

★ 最小均方演算法
★ 類比乘法器
★ 切換式電容積分器

關鍵字(英)

★ Least Mean Square algorithm
★ analog multiplier
★ switched-capacitor integrator

論文目次

目錄
摘要 i
Abstract ii
致謝 iv
圖目錄 vii
表目錄 xi
第1章緒論 1
1-1 研究背景 1
1-2 研究動機 1
1-3 論文貢獻 2
1-4 論文架構 2
第2章迴音消除器架構概論 3
2-1 迴音消除器系統概要 3
2-2 數位濾波器架構介紹 4
2-2-1 數位有限脈衝響應濾波器電路架構 4
2-2-2 數位無限脈衝響應濾波器電路架構 5
2-3 類比濾波器架構介紹 7
2-3-1 類比有限脈衝響應濾波器電路架構 7
2-3-2 類比無限脈衝響應濾波器電路架構 9
2-4 自適應演算法介紹 10
2-4-1 粒子群最佳化演算法 10
2-4-2 最小均方演算法 13
第3章系統規格與電路架構 14
3-1 系統環境 14
3-2 演算法選擇 17
3-3 電路架構 20
3-4 規格 22
3-5 乘法器 28
3-6 切換式電容積分器 34
3-7 非重疊時脈產生電路 40
第4章佈局與模擬結果 42
4-1 電路佈局與考量 42
4-2 模擬結果 43
第5章量測 80
5-1 量測考量 80
5-2 量測結果 83
第6章結論 87
6-1 文獻比較 87
6-2 結論與未來展望 88
參考文獻 89

參考文獻

[1] IEEE Standard for Ethernet Amendment 7: Media Access Control Parameters, Physical Layers, and Management Parameters for 2.5 Gb/s and 5 Gb/s Operation, Types 2.5GBASE-T and 5GBASE-T.
[2] Tai-Cheng Lee and B. Razavi, "A 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire," IEEE Journal of Solid-State Circuits, vol. 36, no. 3, pp. 366-373, March 2001.
[3] N. Verhoeckx, H. van den Elzen, F. Snijders and P. van Gerwen, “Digital echo cancellation for baseband data transmission,” IEEE Trans. on Acoustics, Speech, and Signal Processing, Vol.27, pp. 768-781, Dec 1979.
[4] J. Ebrahimi, S. H. Hosseinian and G. B. Gharehpetian, "Unit Commitment Problem Solution Using Shuffled Frog Leaping Algorithm," IEEE Transactions on Power Systems, vol. 26, no. 2, pp. 573-581, May 2011.
[5] A. Abousaada, T. Aboulnasr and W. Steenaart, "An echo tail canceller based on adaptive interpolated FIR filtering," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 39, no. 7, pp. 409-416, July 1992.
[6] Fan Hong and W. K. Jenkins, "An investigation of an adaptive IIR echo canceller: advantages and problems," IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 36, no. 12, pp. 1819-1834, Dec. 1988.
[7] D. L. Jones, "Learning characteristics of transpose-form LMS adaptive filters," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 39, no. 10, pp. 745-749, Oct. 1992.
[8] M. Faust and C. -H. Chang, "Optimization of structural adders in fixed coefficient transposed direct form FIR filters," 2009 IEEE International Symposium on Circuits and Systems, Taipei, Taiwan, 2009, pp. 2185-2188.
[9] P. Pawłowski, R. Długosz and A. Dąbrowski, "Switched-capacitor finite impulse response rotator filter," 2020 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA), Poznan, Poland, 2020, pp. 133-137.
[10] S. Park, D. Shin, K. -J. Koh and S. Raman, "A Low-Power, High-Linearity Wideband 3.25 GS/s Fourth-Order Programmable Analog FIR Filter Using Split-CDAC Coefficient Multipliers," IEEE Transactions on Microwave Theory and Techniques, vol. 68, no. 4, pp. 1576-1590, April 2020.
[11] J. B. Monteiro and A. Petraglia, "A 0.8/spl mu/m CMOS programmable IIR SC filter," 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), Vancouver, BC, Canada, 2004, pp. I-869.
[12] J. Kennedy and R. Eberhart, "Particle swarm optimization," Proceedings of ICNN′95 - International Conference on Neural Networks, 1995.
[13] B. Widrow, J. M. McCool, M. G. Larimore and C. R. Johnson, "Stationary and nonstationary learning characteristics of the LMS adaptive filter," Proceedings of the IEEE, vol. 64, no. 8, pp. 1151-1162, Aug. 1976.
[14] V. J. Mathews and Z. Xie, "Stochastic gradient adaptive filters with gradient adaptive step sizes," International Conference on Acoustics, Speech, and Signal Processing, Albuquerque, NM, USA, 1990, pp. 1385-1388 vol.3.
[15] P. Torkzadeh and M. Atarodi, "Channel Charge Injection analysis and its modeling in z-domain for switched-capacitor integrators," 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, Cancun, Mexico, 2009, pp. 126-129.
[16] N. B. Modi and P. P. Gandhi, "Four quadrant analog multiplier with VCVS in deep-submicron technology," 2013 IEEE Conference on Information & Communication Technologies, 2013, pp. 1091-1094.
[17] A. Satapathy, S. K. Maity and S. K. Mandal, "A flipped voltage follower based analog multiplier in 90nm CMOS process," 2015 International Conference on Advances in Computer Engineering and Applications, 2015, pp. 628-631.
[18] I. Aloui, N. Hassen and K. Besbes, "±0.75V Four Quadrant Analog Multiplier in Current Mode," 2018 15th International Multi-Conference on Systems, Signals & Devices (SSD), 2018, pp. 1045-1050.
[19] S. Hadidi and A. Hassanzadeh, "An Ultra-Low-Power and High-Gain Four-Quadrant Analog Multiplier Based on Dynamic Threshold MOSFET (DTMOS)," 2020 28th Iranian Conference on Electrical Engineering (ICEE), Tabriz, Iran, 2020, pp. 1-5.
[20] S. I. Khan and S. A. Mahmoud, "Highly Accurate Subthreshold Four Quadrant Multiplier for Biomedical Teager Energy Operator Circuits," 2020 Advances in Science and Engineering Technology International Conferences (ASET), Dubai, United Arab Emirates, 2020, pp. 1-4.
[21] S. A. Enche Ab Rahim, M. A. Ismail, A. I. Abdul Rahim, M. R. Yahya and A. F. Awang Mat, "A wide gain-bandwidth CMOS fully-differential folded cascode amplifier," 2010 International Conference on Electronic Devices, Systems and Applications, 2010, pp. 165-168.
[22] D. Calderón-Preciado, F. Sandoval-Ibarra, J. G. García-Sánchez and S. Ortega-Cisneros, "Analysis of an OTA/output stage for a SC integrator in a Hybrid ΣΔ Modulator," 2016 IEEE Biennial Congress of Argentina (ARGENCON), 2016, pp. 1-4.
[23] T. V. Prasula and D. Meganathan, "Design and simulation of low power, high gain and high bandwidth recycling folded cascode OTA," 2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN), 2017, pp. 1-6.
[24] R. Kammari, J. Gundla, S. Boyapati and V. S. R. Pasupureddi, "Modeling and Design of A Compact Low Power Folded Cascode OpAmp With High EMI Immunity," IEEE Transactions on Electromagnetic Compatibility, vol. 64, no. 2, pp. 595-598, April 2022.
[25] A. Ranjan and R. Chauhan, "An Enhancement of Recycling Folded Cascode Amplifier Using Potential Divider Method," 2022 13th International Conference on Computing Communication and Networking Technologies (ICCCNT), Kharagpur, India, 2022, pp. 1-6.

指導教授

薛木添(Muh-Tian Shiue)

審核日期

2023-8-10

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