適用在通訊應用知可參數化數位信號處理器資料通路設計

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姓名

鄧君賢(Jun-Xian Teng) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

適用在通訊應用知可參數化數位信號處理器資料通路設計
(Parameterized and Embedded DSP Datapath for Communication Systems)

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摘要(中)

摘要
隨著市場的變化越來越快速，晶片設計的時程也變的越來越緊迫，為了能夠在限定時程內完成系統設計，數位訊號處理器可以協助設計人員快速建立系統，然而，全客戶化設計雖耗時較多，卻能夠提供的一定程度的效能提昇。
為了能夠在限定的時間內完成符合目前市場需求以及未來效能提昇的設計，我們提出了可參數化數位訊號處理器設計方法論，並且完成了一系列針對通訊系統設計的特殊功能單元（Special Function Block）。
在資料通路設計(datapath)上，我們針對通訊系統實際應用上對輸入訊號精密度要求的特性，設計了可處理半長度輸入(sub-word input)類型的相乘累加單元，為了能夠利用相同的硬體完成全長度輸入(full-word input)類型的相乘累加，同時兼顧防溢位(overflow)的防護位元(guard bit)運作，我們針對這方面的資料通路設計作了探討。
而在針對通訊系統的應用上，我們提出的可參數化數位訊號處理器可在資料通路及資料讀取上搭配傅立葉運算。另外在相關性運算（correlation）的方面，我們提出了一個為相關性運算所設計的特殊功能單元設計，以及這個特殊功能單元如何與數位訊號處理器共用資料匯流排和加快運算速度。最後，整個可參數化數位處理器的設計流程藉由Visual Basic和C語言所撰寫程式整合在一起。如此一來，藉由可參數化數位訊號處理器搭配上特殊化模組，我們所提出的這種設計方法能夠幫助設計人員建立一個設計環境能夠同時兼顧系統建立的時程以及未來系統效能的提昇。

摘要(英)

Abstract
In this thesis, a parameterized DSP datapath design and the parameterized DSP design flow are carried out. The proposed parameterized DSP is composed of DSP itself along with special blocks designed for communication systems. We term this kind processor as parameterized ASIC/DSP core. In the DSP datapath design, a subword MAC path with consideration of guard bit allocation is built for application in two different precision situations. Other than the subword MAC path, a correlator designed for WCDMA system is proposed. The correlator is designed to cooperate with DSP and share the same data bus with DSP.
A parameterized DSP design flow is also proposed in this thesis, we divide issues during a parameterized DSP develop process into three sorts : arguments, control schemes, and structures. These issues are introduced and solved by establish an parameterized DSP generator, which is designed in Visual Basic and C language.

關鍵字(中)

★ 相關性計算
★ 可參數化
★ 數位信號處理器
★ 資料通路
★ 半長度乘法器

關鍵字(英)

★ datapath
★ DSP
★ subword multiplier
★ correlator
★ parameterized
★ configurable

論文目次

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Evolution of Communication DSP Processors 3
1.3 Wireless Communication-Specific DSP Architecture 5
1.4 Thesis Organization 6
Chapter 2 The Design of Data Path 7
2.1 Introduction 7
2.2 Overall Structure of NCU_DSP_2002 8
2.3 Status Registers 11
2.4 The ALU 12
2.5 The Default MAC Path 14
2.6 The Dual MAC Path 16
2.7 The Subword MAC Path 17
2.7.1 The Subword Multiplier 17
2.7.2 Sign Extension Consideration 20
2.8 The Subword Accumulator 25
2.8.1 Guardbit Allocation Consideration 26
2.8.2 Structure of Subword MAC Design 26
2.9 Dual MAC Unit Suitable for Subword 29
2.10 Summary 30
Chapter 3 FFT and Correlation 31
3.1 Introduction of FFT 31
3.2 FFT Implementation With NCU_DSP 32
3.2.1 Bit Reversal Addressing Mode 32
3.2.2 Complex Number Computation 33
3.3 Introduction of Correlation 35
3.4 Design of Correlator Special Block Design 36
3.4.1 Spreading Code and scrambling code 36
3.4.2 Low Power Correlator Design 37
3.4.3 Cooperation with NCU_DSP_2002 40
3.5 Summary 46
Chapter 4 Parameterized Design Flow 47
4.1 Parameterized Design Flow of NCU_DSP_2002 47
4.1.1 Special Block Identity 47
4.1.2 Parameters Identity 52
4.2 DSP Datapath Parameterized Design Flow 53
4.2.1 Arguments Dependent on Parameters 54
4.2.2 Control Schemes Dependent on Parameters 54
4.2.3 Structures Dependent on Parameters 55
4.3 Summary 57
Chapter 5 Implementation Results 58
5.1 Implemented Parameterized Design Flow 58
5.2 Synthesis Results 62
5.2.1 First Version of our DSP Core — NCU_DSP 65
5.3 Test Consideration 66
5.4 Benchmark Simulation 67
Chapter 6 Conclusion and Future Works 69
Reference 71

參考文獻

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指導教授

周世傑(Shyh-Jye Jou)

審核日期

2002-7-15

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