具接收端前饋式等化器補償之 10 Gb/s全速率接收端電路

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姓名

王遠(Yuan Wang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具接收端前饋式等化器補償之 10 Gb/s全速率接收端電路
(A 10 Gb/s Full-Rate Receiver with RX-FFE Compensation)

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至系統瀏覽論文 (2027-8-1以後開放)

摘要(中)

隨著科技的進步，資料傳輸速率不斷提升，高速串列傳輸技術漸漸取代掉傳統並列傳輸方式，例如 HDMI、 Displayport、 USB、 SATA、 PCI-Express等。但因通道頻寬並未隨之上升，造成資料經過傳輸通道的衰減越為嚴重，因此將等化器應用於接收端，以補償資料來使訊號完整度上升被廣泛應用於近年來的發展。

本論文提出一接收端前饋式等化器架構，其利用類比延遲電路將輸入訊號做出不同時間的延遲，並針對相對應之第一級前游標資料符碼間干擾乘上權重係數來進行消除。與傳統架構相比，其不需使用到時脈進行取樣和緩衝器電路，因此在維持資料振幅的同時，也可降低功率消耗。本論文在等化器架構上整合連續時間線性等化器、前饋式等化器及一階離散時間決策回授等化器來進行補償消除符碼間干擾，以達到降低硬體複雜度與整體功率消耗的效果來補償資料。

本論文使用TSMC 40 nm (TN40G) 1P10M CMOS製程實現，電路操作電壓為 0.9 V輸入資料採用 10 Gb/s之 NRZ資料訊號，輸入時脈採用全速率 10 GHz時脈訊號，等化器可補償之通道衰減範圍為 7 dB至 33 dB，於佈局後模擬在通道衰減 7 dB時，補償後之眼圖眼高改善 22 佈局後模擬在通道衰減 33 dB時，補償後之眼圖眼高改善 47 %。整體功率消耗為 18.88 mW。 45nm/40nm微縮後之晶片面積為 1.060 mm2，其中核心電路面積為 0.026 mm2。

摘要(英)

With the advancement of technology, the data transmission rate has been continuously improved. High-speed serial link technology has gradually replaced the traditional parallel transmission, such as HDMI, Displayport, USB, SATA, PCI-Express. However, the attenuation of the data through the transmission channel is more serious, because the channel bandwidth does not increase accordingly. Therefore, the equalizer is widely used at receiver to compensate the data to increase the signal integrity.

This thesis proposed a feed-forward equalizer at the receiver, the inter-symbol-interference (ISI) can be eliminated by using the analog delay circuit to delay the input signal, and multiplies a weight coefficient. Compared with the traditional architecture, it does not need to use the clock for sampling and buffer circuits, so the power consumption can be reduced while maintaining the data amplitude. In addition, the continuous time linear equalizer (CTLE)、 feed-forward equalizer (FFE) and 1-tap discrete-time decision feedback equalizer (1-tap DT-DFE) are be used in data compensation. As the result, the proposed adaptive receiver system not only reduce the complexity of hardware and power consumption, but also can be widely used for 7-33 dB channel loss application.

This chip is fabricated by TSMC 40 nm (TN40G) 1P10M CMOS process. In simulation result, the input is 10 Gb/s PRBS7 NRZ data, and the 10 GHz full rate clock be adopted. In 7-dB channel loss, 22 % improvement in eye height after compensation. In 33-dB channel loss, 47 % improvement in eye height after compensation. The overall power consumption of whole receiver consumes 18.88 mW at 0.9 V supply voltage. The chip area with 40 nm which is scaling down by 45 nm is 1.060 mm2 and core area is 0.026 mm2.

關鍵字(中)

★ 接收端前饋式等化器

關鍵字(英)

論文目次

摘要 i
Abstract ii
目錄 iv
圖目錄 vii
表目錄 xi
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 4
第2章高速串列傳輸之訊號完整度 5
2.1 基本觀念 5
2.1.1 隨機二位元資料特性 5
2.1.2 資料格式 7
2.1.3資料編排形式 7
2.1.4傳輸線理論 9
2.2 抖動分析 15
2.2.1 隨機抖動 (RJ) 16
2.2.2 定量性抖動 (DJ) 17
2.2.2.1 資料相關抖動 17
2.2.2.2 責任週期失真 (DCD) 18
2.2.2.3 週期性抖動 (PJ) 18
2.3 單一位元脈衝響應與等化器之關係 20
2.4 眼圖分析 23
2.5 誤碼率 24
第3章等化器與自適應系統之背景介紹 27
3.1 等化器的種類 27
3.1.1 連續時間線性等化器 (CTLE) 28
3.1.2 決策回授等化器決策回授等化器(DFE) 29
3.1.3 前饋式等化器前饋式等化器(FFE) 31
3.2 自適應系統自適應系統 33
3.2.1 最小均方演算法最小均方演算法(LMS) 33
3.2.2 SS-LMS之技術應用於等化器之技術應用於等化器 36
3.2.3 SS-LMS之之限制限制 39
3.2.4 逼零演算法逼零演算法(Zero-Forcing Algorithm) 40
3.3 接接收端電路文獻探討收端電路文獻探討 42
3.3.1 多階數決策回授等化器多階數決策回授等化器
(Multi-Tap DFE) 42
3.3.2 有限有限/無限脈衝響應決策回授等化器無限脈衝響應決策回授等化器(FIR/IIR DFE) 43
3.3.3 前饋式前饋式/決策回授等化器決策回授等化器(FFE/DFE) 44
3.4 比較與討論比較與討論 45

第4章自適應接收端之架構設計與實現自適應接收端之架構
設計與實現 46
4.1 電路架構電路架構 46
4.2 操作說明操作說明 48
4.2.1 前饋式等化器前饋式等化器(FFE)自適應系統自適應系統 48
4.2.2 資料路徑之單一位元脈衝響應資料路徑之單一位元脈衝響應 50
4.3 行為模擬行為模擬 52
4.4 子電路設計實現與模擬分析子電路設計實現與模擬分析 54
4.4.1 連續時間線性連續時間線性等化器等化器(CTLE) 54
4.4.2 一階離散時間決策回授等化器一階離散時間決策回授等化器
(DFE) 56
4.4.3 前饋式等化器自適應系統前饋式等化器自適應系統(FFE Adaptive System) 57
4.4.4 自適應系統自適應系統(Adaptive System) 62
4.4.4.1訊號序列偵測器訊號序列偵測器(Data Pattern Detector, DPD) 63
4.4.4.2自適應演算系統自適應演算系統
(Adaptive Algorithm System) 64
4.4.4.3增益調整系統增益調整系統
(Gain Adjustment System, GAS) 65
4.4.4.4迴路切換機制迴路切換機制(Loop Switch Mechanism) 67
4.4.5 時脈與資料回復電路時脈與資料回復電路(CDR) 68
4.5 模擬結果模擬結果 72

4.5.1 通道模型通道模型 72
4.5.2 佈局前模擬佈局前模擬(Pre-Layout Simulation) 74
4.5.2.1短通道模擬短通道模擬(Channel Loss = 7 dB @ 5 GHz) 74
4.5.2.2長通道模擬長通道模擬(Channel Loss = 33 dB @ 5 GHz) 77
4.5.3 佈局後模擬佈局後模擬(Post-Layout Simulation) 80
4.5.3.1短通道模擬短通道模擬(Channel Loss = 7 dB @ 5 GHz) 80
4.5.3.2長通道模擬長通道模擬(Channel Loss = 33 dB @ 5 GHz) 83
4.5.4 模擬模擬結果統整及比較結果統整及比較 86
4.5.4.1佈局前模擬佈局前模擬 86
4.5.4.2佈局後模擬佈局後模擬 88

第5章晶片佈局與量測晶片佈局與量測 90
5.1 電路佈局電路佈局 90
5.1.1 晶片封裝晶片封裝 91
5.1.2 佈局與電源配置佈局與電源配置 93
5.2 量測考量量測考量 94
5.2.1 量測環境量測環境 94
5.2.2 高速輸入緩衝器高速輸入緩衝器 95
5.2.3 高速輸出緩衝器高速輸出緩衝器 97
5.3 規格比較表規格比較表 98

第6章結論結論 100
6.1 結論結論 100
6.2 未來研究方向未來研究方向 101
參考文獻 102

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2023-1-4

推文