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姓名 蔡凱翔(Kai-Hsiang Tsai) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 半橋氮化鎵驅動電路和功率電晶體積體化設計和其降壓器應用
(A Fully Integrated GaN Half-Bridge IC for Buck Converter)檔案 [Endnote RIS 格式]
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至系統瀏覽論文 ( 永不開放)
摘要(中) 氮化鎵(GaN)電晶體由於其閘極電荷小，且內部沒有寄生pn 二極體(body diode)，因 此可以達到非常快的切換速度與低硬切換損耗，非常適合應用於高壓電源轉換器。隨著 氮化鎵製程平台逐漸成熟，水平結構的氮化鎵電晶體能在單一晶片上實現閘極驅動器與 功率開關的積體化，從而降低電路的鎊線寄生效應。
本篇論文將氮化鎵功率開關與閘極驅動器積體化成半橋(half-bridge)晶片，並利用氮 化鎵電晶體反向傳導之特性將自舉開關同時進行積體化。透過分析功率開關切換過程的 能量轉換評估半橋晶片的損耗，並透過傳導損耗與輸出電荷(Qoss)之間的權衡選擇功率開 關的尺寸，並設計其閘極驅動器，在有足夠的驅動能力下也同時抑制閘極振鈴。
最後將此半橋晶片應用於降壓轉換器，此晶片能操作在500 kHz ~ 1 MHz 的切換頻 率，在切換頻率為1 MHz 時，可以實現48 V 到24 V 與12 V 的電壓轉換。操作於500 kHz 時可以實現100 V 到48 V 的電壓轉換。在48 V 到24 V 的電壓轉換與0.4 A 的輸出 電流下能達到91 %的峰值效率。摘要(英) Gallium Nitride (GaN) transistors are highly suitable for high-voltage power converters due to their low gate charge and absence of a parasitic pn diode (body diode) within. These characteristics allow for rapid switching speeds and low switching losses, making them ideal for high-voltage power conversion applications. With the maturation of GaN fabrication processes, GaN transistors with lateral structures can be monolithically inte grated on a single chip, combining gate drivers and power switches to reduce circuit parasitics.
This paper integrates gallium nitride power switches and gate drivers into a half-bridge chip and utilizes the reverse conduction characteristics of gallium ni tride transistors to integrate the bootstrap switch simultaneously. The losses of the half-bridge chip are evaluated by analyzing the energy conversion during power switch transitions. The sizing of the power switches is chosen through a trade-off between conduction losses and output charge (Qoss ), and their gate drivers are designed to provide sufficient drive capability and suppress gate ringing.
Finally, this half-bridge chip is applied to a Buck converter. The chip can operate at switching frequencies between 500 kHz and 1 MHz. At a switching frequency of 1 MHz, it can achieve voltage conversions from 48 V to 24 V and 12 V. When operating at 500 kHz, it can achieve a voltage conversion from 100 V to 48 V. At a voltage conversion from 48 V to 24 V and an output current of 0.4 A, it can achieve a peak efficiency of 91%.關鍵字(中) ★ 氮化鎵
★ 閘極驅動器
★ 降壓轉換器
★ 半橋關鍵字(英) ★ Gallium Nitride
★ gate driver
★ Buck converter
★ half-bridge論文目次 目錄
摘要 .................................................................................................................................... II
Abstract .............................................................................................................................III
致謝 .................................................................................................................................. IV
目錄 ....................................................................................................................................V
圖目錄 ............................................................................................................................ VIII
表目錄 ............................................................................................................................XIV
第一章 緒論 ...................................................................................................................... 1
1.1 前言 ..................................................................................................................... 1
1.2 P 型閘極電晶體與其驅動器的挑戰 ................................................................... 2
1.2.1 蕭特基與歐姆P 型閘極氮化鎵電晶體和其閘極驅動器之文獻回顧 .. 4
1.2.2 蕭特基與歐姆P 型閘極氮化鎵電晶體之差異 ...................................... 7
1.2.3 蕭特基P 型閘極電晶體硬切換損耗之論文回顧 .................................. 8
1.3 積體化氮化鎵驅動器與功率電晶體之重要性 ............................................... 10
1.3.1 全氮化鎵(all-GaN)製程平台之文獻回顧 ............................................ 11
1.3.2 積體化氮化鎵驅動器與功率電晶體之論文回顧 ................................ 13
1.4 研究動機與目的 ............................................................................................... 15
1.5 論文架構 ........................................................................................................... 16
第二章 氮化鎵積體電路製程平台的選擇與功率電晶體和閘極驅動器之設計 ........ 18
2.1 前言 ................................................................................................................... 18
2.2 高電壓氮化鎵製程平台 ................................................................................... 18
2.3 閘極驅動器原理與電路架構 ........................................................................... 20
2.3.1 閘極驅動器與電壓準位提升電路架構與設計 .................................... 21
2.3.2 DCFL 反向器與緩衝器之電晶體尺寸設計 .......................................... 22
2.4 最小功率開關通道寬度與所需驅動電流之設計 ........................................... 23
VI
2.4.1 氮化鎵功率電晶體之切換機制 ............................................................ 24
2.4.2 最小功率電晶體通道寬度選擇 ............................................................ 26
2.4.3 功率電晶體之驅動電流計算 ................................................................ 28
2.5 DE Driver 設計 .................................................................................................. 29
2.5.1 快速切換導致下橋功率開關誤啟動與過負閘極偏壓 ........................ 32
2.5.2 上橋功率開關開啟過程之振鈴 ............................................................ 35
2.5.3 回沈電晶體之導通損耗 ........................................................................ 38
2.6 本章總結 ........................................................................................................... 39
第三章 半橋氮化鎵驅動電路和功率氮化鎵電晶體積體化設計和其降壓器應用模擬
分析 .......................................................................................................................................... 40
3.1 自舉式電路(bootstrap circuit) .......................................................................... 40
3.1.1 氮化鎵蕭特基電晶體的反向傳導特性與自舉二極體積體化 ............ 41
3.1.2 二極體通道寬度與電容選擇 ................................................................ 42
3.2 降壓電路架構與原理 ....................................................................................... 45
3.2.1 降壓電路之被動元件選擇 .................................................................... 47
3.2.2 同步整流半橋降壓轉換器與外部續流二極體 .................................... 50
3.3 功率開關損耗與切換時的能量轉換 ............................................................... 51
3.3.1 功率開關損耗計算 ................................................................................ 51
3.3.2 半橋電路之功率開關損耗 .................................................................... 52
3.4 寄生電容和導通電阻之權衡與功率開關尺寸的選擇 ................................... 57
3.4.1 不同通道寬度的儲存電荷與導通電阻之關係 .................................... 58
3.4.2 寄生電容與導通電阻之權衡 ................................................................ 59
3.4.3 功率開關尺寸的選擇 ............................................................................ 65
3.5 本章總結 ........................................................................................................... 65
第四章 電路實現 ............................................................................................................ 66
4.1 模擬結果 ........................................................................................................... 66
VII
4.1.1 前模擬 .................................................................................................... 67
4.1.2 晶片佈局 ................................................................................................ 73
4.1.3 後模擬 .................................................................................................... 76
4.2 晶片印刷電路板建立 ....................................................................................... 79
4.3 晶片量測環境建立 ........................................................................................... 83
4.4 晶片量測結果 ................................................................................................... 84
4.5 量測結果討論與分析 ....................................................................................... 90
4.5.1 Corner 模擬與量測結果比較與討論 ..................................................... 90
4.5.2 積體化自舉開關與使用外部自舉二極體比較與討論 ...................... 102
第五章 結論與未來展望 .............................................................................................. 106
5.1 結論 ................................................................................................................. 106
5.2 未來展望 ......................................................................................................... 107
5.2.1 改善上橋驅動器的架構 ...................................................................... 107
5.2.2 改善晶片散熱 ...................................................................................... 109
5.2.3 背閘極效應(back-gating effect) .......................................................... 109
5.2.4 上橋Qoss 之過衝電流 .......................................................................... 109
5.2.5 半橋晶片並聯架構 .............................................................................. 109
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