以訊號自參考生成技術實現10 Gb/s單端不歸零訊號等化器應用於高雜訊通道

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蔡騰輝(Teng-Huei Tsai) 查詢紙本館藏

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電機工程學系

論文名稱

以訊號自參考生成技術實現10 Gb/s單端不歸零訊號等化器應用於高雜訊通道
(A 10-Gb/s Single-Ended NRZ Equalizer with Data Self-Referenced Technique for High Noise Channel)

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至系統瀏覽論文 (2029-1-19以後開放)

摘要(中)

隨著近年雲端運算、邊緣運算、人工智慧等資通產業的蓬勃發展，其技術對運算需求快速提升，對資料傳輸速度與環境雜訊複雜度的要求也有所提升。然而高速串列傳輸速度提升，資料受到傳遞距離衰減影響越為嚴重，雜訊占總體訊號比例也隨所傳遞距離提升迅速放大，訊號品質因此下降，因此等化器如何使訊號在傳輸過程能還原其完整度就顯得十分重要。
本論文提出訊號自參考生成技術，以此來輔助單端輸入資料進行邏輯判斷，其利用資料振幅的電壓位準變換方向來判斷資料極性，並藉由所提出跟蹤-延續-再生比較器解決連續資料問題，實現自參考生成技術，以節省硬體複雜度並提升等化器對高雜訊環境的適應力，並搭配自適應系統，使等化器於高雜訊高通道衰減環境下，自參考生成技術都能輔助自適應系統與DFE對訊號進行合理的補償，並還原出正確的資料，使等化器在使用上能適用於更複雜之環境。
本論文使用TSMC 90 nm (TN90GUTM) 1P9M之CMOS製程來實現，電路操作電壓為1 V，輸入之資料速率為10 Gbps之單端NRZ 資料訊號，輸入時脈採用單端5 GHz 時脈訊號，並藉由內部電路生成半速率差動5 GHz 時脈訊號，等化器於含有雜訊之使用環境最高可使用通道衰減為24dB，當輸入資料振幅為250mV時，最高可抵禦之低頻正弦波(100MHz)雜訊振幅為50mV，經自參考生成技術等化器還原後之資料速率為10 Gbps之單端NRZ 資料訊號，於佈局後模擬在通道衰減14 dB 時，還原後之資料抖動峰對峰值為27.63 ps；佈局後模擬在通道衰減24 dB時，還原後之資料抖動峰對峰值為22.51 ps。整體功率消耗為43.97 mW，其中等化器CTLE 、1-tap SR DFE與跟蹤-延續-再生比較器之功耗為19.73 mW，自適應系統之功耗為24.24 mW。整體面積為0.9×0.9 mm2，其中核心電路之面積約為0.103 mm2。

摘要(英)

With the rapid development of information and communication industries such as cloud computing, edge computing, and artificial intelligence in recent years, the demand for computing power has increased rapidly, and the requirements for data transmission speed and environmental noise complexity have also increased. However, as the transmission speed increases, the data is more seriously affected by the transmission distance, and the proportion of noise in the total signal also increases, resulting in a decrease in signal quality. Therefore, it is very important for equalizers to restore the integrity of the signal in the transmission process.
This paper proposes a signal Self-Reference generation technology to assist in the logical judgment of single-ended input data. It uses the voltage level change direction of the data amplitude to judge the data polarity. By using an innovative Track-Extend-Regenerate Slicer to solve the continuous data problem, the self-reference generation technology is realized to save hardware complexity and improve the adaptability of the equalizer to high-noise environments. In addition, it is combined with an adaptive system to ensure that the Self-Reference generation technology can assist the adaptive system and DFE to compensate the signal reasonably in high noise and high channel-loss environments, and restore the correct data.
This paper is implemented using TSMC 90 nm (TN90GUTM) 1P9M CMOS process. The circuit operating voltage is 1 V. The input data rate is 10 Gbps single-ended NRZ data signal. The input clock adopts a single-ended 5 GHz clock signal, and a half-rate differential 5 GHz clock signal is generated by the internal circuit. The equalizer can be used in a noisy environment with a maximum channel-loss of 24 dB. When the input data amplitude is 250 mV, the maximum low-frequency sine wave (100 MHz) noise amplitude that can be resisted is 50 mV. After the signal Self-Reference generation technology equalizer restores the 10 Gbps single-ended NRZ data signal, the post-layout simulation shows that the peak-to-peak jitter of the restored data is 27.63 ps when the channel-loss is 14 dB. The post-layout simulation shows that the peak-to-peak jitter of the restored data is 22.51 ps when the channel-loss is 24 dB. The overall power consumption is 43.97 mW, of which the power consumption of the equalizer CTLE, 1-tap SR DFE, and Track-Extend-Regenerate Slicer is 19.73 mW, and the power consumption of the adaptive system is 24.24 mW. The overall area is 0.9 × 0.9 mm2, of which the area of the core circuit is approximately 0.103 mm2.

關鍵字(中)

★ 等化器
★ 自參考技術
★ 序列器/解除序列器
★ 雜訊
★ 不歸零訊號

關鍵字(英)

★ Equalizer
★ Self-Referenced
★ SerDes
★ Noise
★ NRZ

論文目次

摘要 i
Abstract ii
誌謝 iv
目錄 v
圖目錄 viii
表目錄 xiii
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 5
第2章高速串列傳輸之訊號完整性 6
2.1 基本觀念 6
2.1.1 隨機二位元資料特性 6
2.1.2 資料格式與編排形式 7
2.1.3 傳輸線理論[13] 10
2.2 抖動分析 17
2.2.1 隨機抖動(Random Jitter, RJ) 18
2.2.2 定量性抖動(Deterministic Jitter, DJ) 19
2.2.2.1 週期性抖動(Period Jitter, PJ) 19
2.2.2.2 工作週期失真(Duty Cycle Distortion, DCD) 19
2.2.2.3 資料相關抖動(Data Dependent Jitter, DDJ) 20
2.3 單一位元脈衝響應與等化器之關係 21
2.4 眼圖分析 24
2.5 誤碼率[1] 25
第3章各型等化器之背景簡介 28
3.1 等化器電路的總類 28
3.1.1 連續時間線性等化器(CTLE) 29
3.1.2 決策回授等化器(DFE) 31
3.1.3 前饋式回授等化器(FFE) 34
3.1.4 離散時間線性等化器(DTLE) 35
3.2 自適應機制的種類 36
3.2.1 頻譜平衡技術(Spectrum Balancing Technique) 36
3.2.2 最小均方演算法(LMS) 37
3.2.2.1 SS-LMS之電路架構實現與限制 40
3.2.3 逼零演算法(Zero-Forcing Algorithm) 43
3.2.4 眼廓演算法 44
3.3 單端等化器電路文獻回顧 45
3.3.1 參考電位決策回授等化器(Equalized VREF) 45
3.3.2 非對稱上拉/下拉權重決策回授等化器(Asymmetric DFE) 46
3.3.3 自參考生成技術決策回授等化器(Self-Referenced DFE) 47
3.4 比較與討論 49
第4章自參考生成技術之等化器架構設計與實現 50
4.1 設計流程 50
4.2 電路架構 51
4.3 操作說明 53
4.3.1 等化器補償情況 53
4.3.2 自參考生成技術 54
4.4 行為模擬 57
4.5 系統子電路實現與介紹 60
4.5.1 連續時間線性等化器(CTLE) 60
4.5.2 一階自參考生成技術決策回授等化器(1-Tap SR DFE) 62
4.5.3 自適應演算法(Adaptive Algorithm) 65
4.5.3.1 訊號序列檢測器(Data Pattern Detector) 66
4.5.3.2 自適應演算法(Adaptive Algorithm) 67
4.5.3.3 增益調整電路(Gain Adjuster) 70
4.5.3.4 自適應輔助迴路切換電路(Adaptive Loop Switch) 72
4.6 模擬結果 73
4.6.1 通道模型 73
4.6.2 自參考生成技術之10 Gbps等化器模擬 76
4.6.2.1 佈局前模擬 76
4.6.2.1.1 長通道無雜訊模擬(Channel Loss = 24 dB @ 5 GHz) 76
4.6.2.1.2 長通道有雜訊模擬(Channel Loss = 24 dB @ 5 GHz) 79
4.6.2.1.3 短通道無雜訊模擬(Channel Loss = 14 dB @ 5 GHz) 82
4.6.2.1.4 短通道有雜訊模擬(Channel Loss = 24 dB @ 5 GHz) 85
4.6.2.2 佈局後模擬 88
4.6.2.2.1 長通道無雜訊模擬(Channel Loss = 24 dB @ 5 GHz) 88
4.6.2.2.2 長通道有雜訊模擬(Channel Loss = 24 dB @ 5 GHz) 91
4.6.2.2.3 短通道無雜訊模擬(Channel Loss = 14 dB @ 5 GHz) 94
4.6.2.2.4 短通道有雜訊模擬(Channel Loss = 24 dB @ 5 GHz) 97
4.6.3 模擬結果整理與問題分析 100
第5章晶片佈局與量測考量 102
5.1 電路佈局 102
5.1.1 晶片封裝 103
5.1.2 佈局規劃與電源規劃 105
5.2 量測考量 106
5.2.1 量測環境 106
5.2.2 高頻輸出緩衝器 107
5.2.3 高頻時脈輸入端 108
5.2.4 M8048A ISI通道 109
5.3 規格比較表 110
第6章結論 112
6.1 結論 112
6.2 未來研究方向 113
參考文獻 114
附錄 117

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2024-1-17

推文