| 摘要(英) |
Chip floorplanning is a crucial step in chip design, determining the placement of modules on the chip canvas. A good floorplan minimizes the total wirelength of connections to different modules on the chip. Shorter wires imply less signal delay and lower power consumption, leading to faster and more efficient chip operation. However, considering the modern ICs with millions of transistors, conventional greedy-based or heuristic-based floorplan algorithms often leads to sub-optimal solutions. Reinforcement learning (RL) offers a promising approach to addressing these limitations. It learns through trial and error and guides by rewards, adapting its strategy to find the best solution. This makes RL suitable for tackling complex optimization problems like floorplanning.
This thesis introduces FusionPlanner, a novel model that effectively leverages both local and global information to autonomously create a valid chip layout design. Its performance can surpass or match state-of-the-art methods. It possesses numerous attractive advantages that are absent in previous works. Firstly, previous works on chip floorplanning have typically focused on hard macros. Our work addresses the challenges of handling soft modules by considering the area and connectivity of both soft modules and hard macros. This allows us to produce more accurate floorplans that take into account the full range of soft module options and prevent any overlap with hard macros. Secondly, our work uses a graph-based network training approach that focuses on the effective integration of edge features. Our method combines image features to capture local information and graph features to grasp global information. This integrated approach aims to enhance the perception of local details while capturing a more extensive contextual understanding within the image.
Our experiments demonstrate that our floorplan method can successfully improve the total wirelength of industrial designs with 28nm technology. In addition, our work can reduce the design time of chip floorplanning by considering soft modules earlier in the design process. |
| 參考文獻 |
[1] Alupoaei, Stelian and Srinivas Katkoori. “Net-based force-directed macrocell placement for wirelength optimization.” IEEE Trans. Very Large Scale Integr. Syst. 10 (2002): 824-835.
[2] A. Vidal-Obiols. et al. "Multilevel Dataflow-Driven Macro Placement Guided by RTL Structure and Analytical Methods," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 12, pp. 2542-2555, Dec. 2021.
[3] Cheng, Chung-Kuan et al. “RePlAce: Advancing Solution Quality and Routability Validation in Global Placement.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38 (2019): 1717-1730.
[4] Chang, Fu-Chieh et al. “Flexible Multiple-Objective Reinforcement Learning for Chip Placement.” ArXiv abs/2204.06407 (2022): n. pag.
[5] Cheng, Ruoyu and Junchi Yan. “On Joint Learning for Solving Placement and Routing in Chip Design.” Neural Information Processing Systems (2021).
[6] Chen, Tianshui et al. “Knowledge-Embedded Representation Learning for Fine-Grained Image Recognition.” International Joint Conference on Artificial Intelligence (2018).
[7] Chen, Tung-Chieh and Yao-Wen Chang. “Modern floorplanning based on B/sup */-tree and fast simulated annealing.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25 (2006): 637-650.
[8] Chen, Tung-Chieh and Yao-Wen Chang. “Modern floorplanning based on fast simulated annealing.” ACM International Symposium on Physical Design (2005).
[9] Goldie, Anna and Azalia Mirhoseini. “Placement Optimization with Deep Reinforcement Learning.” Proceedings of the 2020 International Symposium on Physical Design (2020): n. pag.
[10] Ho, Shinn-Ying et al. “An orthogonal simulated annealing algorithm for large floorplanning problems.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 (2004): 874-877.
[11] Kahng, Andrew B. et al. “Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-scale Complex IP Blocks.” ArXiv abs/2304.11761 (2023): n. pag.
[12] Kamiński, Kamil et al. “Rossmann-toolbox: a deep learning-based protocol for the prediction and design of cofactor specificity in Rossmann fold proteins.” Briefings in Bioinformatics 23 (2021): n. pag.
[13] Kingma, Diederik P. and Jimmy Ba. “Adam: A Method for Stochastic Optimization.” CoRR abs/1412.6980 (2014): n. pag.
[14] Kirkpatrick, Scott et al. “Optimization by Simulated Annealing.” Science 220 (1983): 671 - 680.
[15] Lai, Yao et al. “ChiPFormer: Transferable Chip Placement via Offline Decision Transformer.” ArXiv abs/2306.14744 (2023): n. pag.
[16] Lai, Yao et al. “MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learning.” ArXiv abs/2211.13382 (2022): n. pag.
[17] Lin, Yibo et al. “DREAMPIace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.” 2019 56th ACM/IEEE Design Automation Conference (DAC) (2019): 1-6.
[18] Mirhoseini, Azalia et al. “A graph placement methodology for fast chip design.” Nature 594 (2021): 207 - 212.
[19] Oh, Changyong et al. “Bayesian Optimization for Macro Placement.” ArXiv abs/2207.08398 (2022): n. pag.
[20] Schulman, John et al. “Proximal Policy Optimization Algorithms.” ArXiv abs/1707.06347 (2017): n. pag.
[21] Smith, Leslie N.. “Cyclical Learning Rates for Training Neural Networks.” 2017 IEEE Winter Conference on Applications of Computer Vision (WACV) (2015): 464-472.
[22] Shi, Yunqi et al. “Macro Placement by Wire-Mask-Guided Black-Box Optimization.” ArXiv abs/2306.16844 (2023): n. pag.
[23] Tang, Maolin. “A New Greedy Algorithm for VLSI Floorplan Optimization.” 2008 International Conference on Computer Science and Software Engineering 4 (2008): 1126-1129.
[24] Ueda, Kazuhiro et al. “CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 4 (1985): 12-22.
[25] Vaswani, Ashish et al. “Attention is All you Need.” Neural Information Processing Systems (2017).
[26] Vidal-Obiols, Alex et al. “RTL-Aware Dataflow-Driven Macro Placement.” 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE) (2019): 186-191.
[27] Velickovic, Petar et al. “Graph Attention Networks.” ArXiv abs/1710.10903 (2017): n. pag.
[28] Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, and Li Shang. 2022. GraphPlanner: Floorplanning with Graph Neural Network. ACM Trans. Des. Autom. Electron. Syst. 28, 2, Article 21 (March 2023), 24 pages. |
[Endnote RIS 格式]
[相關文章]
[文章引用]
[完整記錄]
[館藏目錄]
至系統瀏覽論文 (2029-3-7以後開放)
plurk
funp
live
udn
HD
myshare
netvibes
friend
youpush
delicious
baidu
Google bookmarks
del.icio.us
hemidemi
facebook
twitter
google
reddit