適用於中頻接收端的類比前級電路設計

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：25

、訪客IP：52.14.142.189

姓名

張用璽(Long-Xi Chang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

適用於中頻接收端的類比前級電路設計
(Analog Front-End Circuits Design for IF Receiver)

相關論文

★ 運算放大器之自動化設計流程及行為模型研究	★ 2.5Gbps光纖收發機設計
★ 高速序列傳輸之量測技術	★ 使用低增益寬頻率調整範圍壓控震盪器之1.25-GHz八相位鎖相迴路
★ 類神經網路應用於高階功率模型之研究	★ 使用SystemC語言建立IEEE 802.3 MAC 行為模組之研究
★ 以回填法建立鎖相迴路之行為模型的研究	★ 一個2V 5GHz CMOS非整數頻率合成器與和差調變器設計
★ 適用於GHz頻段頻率合成器之CMOS電路技術	★ 高速傳輸連結網路的分析和模擬
★ 一個以取樣方式提供可程式化邏輯陣列功能除錯所需之完全觀察度的方法	★ 2.5Gbps CMOS串列式傳輸收發器設計
★ 抑制同步切換雜訊之高速傳輸器	★ 一個3.3V、8位元、每秒150百萬次取樣CMOS 類比數位轉換器
★ 以行為模型建立鎖相迴路之非理想現象的研究	★ 遞迴式類神經網路應用於序向電路之高階功率模型的研究

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

本論文的設計，主要是以中頻接收端通訊系統應用為目標。論文所包含的電路架構計有自動增益回授控制系統，和類比數位轉換器兩大部分。
在自動控制增益迴路方面，為一負回授系統，而其中可調增益放大器的增益值，將由迴路加以控制，用以穩定輸入訊號振幅大小不同變化。也因為其放大電路操作於線性放大區，所以對訊號造成的變形，影響較小，並且在輸入信號100MHz操作下可以擁有30dB的振幅增益控制範圍而輸入信號的振幅範圍是10mVpp到300mVpp振幅大小，同時為了符合現在低電壓下的操作系統，所以是在0.18um製成1.8V的操作電壓下設計，所消耗的功率為21mW。
在類比數位轉換器方面，希望能夠設計出擁有高解析度並且高速的類比數位轉換器為主，以期待能應用在Cable Modem和HDTV的使用上。在設計上類比數位轉換器是採用管線化的方式使操作速率提升。在取樣保持電路上是採用Flip-Around的方式使得在保持模式時的回授因子降到最小，以節省操作放大器的功率消耗。而在電路精確度的考量上，藉由每一位元的重合數位矯正技術，使每一級的誤差容忍度有500mV。在100MS/s的操作頻率下，這個類比數位轉換器擁有10-bit的準確度。此電路設計是在0.18um製成3.3V操作下設計的，所號功率為557mW。

摘要(英)

The project of this thesis is analog front-end circuits design for IF receiver. It concludes two components – an automatic gain control system design and an analog-to-digital system design.
In the automatic gain control system design, this system is a feedback closed loop control system and its gain can be controlled by this feedback closed loop system. Because of this gain control mechanism, the output of the system has constant magnitude with different input magnitude swings, and the output signal will have lower distortion. When input signal is 100MHz, the gain control range of this system is 30dB and the input signal range is from 10mVpp to 300mVpp. The technology is UMC018 process, power supply is 1.8V, and power consumption is 21mW.
In the analog-to-digital converter system design, a 100MSs/s 10-bit pipelined analog-to-digital converter system is designed, and it will used in the cable modem communication system or HDTV. This converter utilizes pipelined architecture to have 100MS/s conversion rate. In sample-and-hold amplifier design, it utilizes the flip-around architecture to have best feedback closed loop factor, so the OP in the sample-and-hold amplifier will cost lower power. The coarse quantizer can tolerate 500mV comparator offset without overflow by digital error correction technique. The effect of process variation in the circuit will be estimated by Monte-Carlo simulation. The technology is TSMC018 process 3.3V CMOS model, power supply is 3.3V, and power consumption is 557mW.

關鍵字(中)

★ 中頻接收端
★ 類比數位轉換器
★ 自動增益控制電路
★ 可變增益放大器
★ 振幅峰值偵測器
★ 取樣保持電路

關鍵字(英)

★ ADC
★ AGC
★ SHA
★ VGA
★ peak detector
★ cable modem

論文目次

Content
Chapter 1 Introduction 1
1.1 Motivations 1
1.2 Research Goals 4
1.3 Thesis Organization 4
Bibliography 6
Chapter 2 AGC Circuit Design 7
2.1 Automatic Gain Control (AGC) System Requirements 8
2.1.1 Mathematical Modeling – VGA 10
2.1.2 Mathematical Modeling – AGC 12
2.2 The AGC Circuits Design 14
2.2.1 Variable Gain Amplifier Design 15
2.2.2 Constant Gain Buffer Design 19
2.2.3 Amplitude Detector Design 20
2.2.4 Integrator Design 24
2.3 The Overall AGC Performance 25
2.4 The Overall AGC Summary 29
Bibliography 31
Chapter 3 SHA Circuit Design 32
3.1 The ADC Structure Overview 33
3.2 Sample-and-Hold Amplifier Circuit Design 36
3.2.1 Full Differential Sample-and-Hold Amplifier Circuit Design 41
3.2.2 The Switch Circuit Design 44
3.2.3 The OP Design 48
3.2.4 The Sample-and-Hold Amplifier Performance 50
Bibliography 54
Chapter 4 ADC Circuit Design 55
4.1 The ADC Structure Overview 56
4.2 1.5-Bit ADC Circuit Design 60
4.2.1 Preamplifier Design 61
4.2.2 Comparator Latch Design 63
4.2.3 Encoder Design 64
4.3 MDAC Circuit Design 65
4.4 Latch Circuit Design 70
4.5 Digital Correction Adder Circuit Design 71
4.6 Non-overlapping Clock Generator Circuit Design 72
4.7 Overall ADC Result 74
Bibliography 76
Chapter 5 Conclusions 77

參考文獻

[1] P.C. Huang, “Analog Front-End Architecture and Circuit Design Techniques for High Speed Communication VLSIs, ” PH.D. dissertation in National Central University, June 1998.
[2] Curtis Ling, Raymond Montemayor, Alberto Cicalini, Kevin Wang, Lars Jansson, Lars Mucke, Pushp Trihka, S.V. Kishore, “A Low-Power Integrated Tuner for Cable-Telephony Applications,” in ISSCC Digest of Technical Papers, Feb 2002.
[3] Lionel J. D’Luna, Loke K. Tan, Dean Mueller, Joe L. Laskowski, Kelly Cameron, Jind-Yen Lee, David Gee, Jason S. Monroe, Honman S. Law, Jason Chang, Myles H. Wakayama, Tom Kwan, Chi-Hung Lin, Aaron Bbuchwald, Tarek Kaylani, Fang Lu, Tom Spieker, Robert Hawley, Henry Samueli,”A Single-Chip Universal Cable Set-Top Box/Modem Transceiver,” IEEE J. of Solid-State Circuits, vol. 34, pp. 1647-1660, Nov. 1999.
[4] Tatsuji Matsuura, Takashi Nara, Tatsuya Komatsu, Eiki Imaizumi, Toshihiro Matsutsuru, Ryutaro Horita, Haruto Katsu, Shintaro Suzumura, Kazuo Sato, “A 240Mb/s 1W CMOS EPRML Read Channel LSI for Hard Disk Drives”, in ISSCC Digest of Technical Papers, Feb 1998.
[5] Tatsuji Matsuura, Takashi Nara, Tatsuya Komatsu, Eiki Imaizumi, Toshihiro Matsutsuru, Ryutaro Horita, Haruto Katsu, Shintaro Suzumura, Kazuo Sato, “A 240-Mb/s, 1W CMOS EPRML Read-Channel LSI Chip Using an Interleaved Subranging Pipline A/D Converter”, IEEE J. of Solid-State Circuits, vol. 33, pp. 1840-1850, Nov. 1998.
[6] John Khoury and Hai Tao ,”Data Converters foe Communication Systems,” in IEEE Communications Magazine, October 1998.
[7] Behzad Razavi, “ Design of Analog CMOS Integrated Circuits”, McGRAW-HILL, 2000.
[8] C.K. Wang and P.C. Huang, “ An Automatic Gain Control Architecture for SONET OC-3 VLSI”, IEEE Trans. On Circuits and Systems, pt II, vol. 44, pp. 779-783, Sep, 1997.
[9] R. Harjani, “A Low-Power CMOS VGA for 50Mb/s Disk Drive Read Channel”, IEEE Trans. On Circuits and Systems II, vol. 42, no. 6, pp. 370-376, June 1995.
[10] C. Srinivasan and K. Radhakrishna Rao, “A 20MHz CMOS Variable Gain Amplifier”, IEEE 9th International Conference on VLSI Design, January, 1996.
[11] S. Tadjpour, F. Behbahani, and A.A. Abidi, “A CMOS Variable Gain Amplifier for a Wideband Wireless Receiver”, IEEE Symposium on VLSI Circuits Digest to Technical Papers, 1998.
[12] P.C. Huang, L.Y. Chiou and C.K. Wang, “A 3.3V CMOS Wideband Exponential Control Variable Gain Amplifier”, IEEE Symp. On Circuits and System pp. 00-00, Monterey USA, May 1998.
[13] R. Gomez and A.A. Abidi, “A 50MHz CMOS Variable Gain Amplifier for Magnetic Data Storage Systems”, IEEE Journal of Solid-State Circuits, vol. 27, no. 6, June 1992.
[14] Z.H. Wang, “Full-Wave Precision Rectification that is Performed in Current Domain and Very Suitable for CMOS Implementation”, IEEE Trans. On Circuits and System, pt-I, vol. 39, no. 6, pp. 456-462, June 1992.
[15] Jason Hsien, ”Nyquist-Rate A/D Converter Design”, CIC Training Manual, January 2003.
[16] D.A. Johns and K. Martin, “Analog Integrated Circuit Design”, John Wiley and Sons, Inc. , 1997.
[17] Ren-Hong Luo, “A 3.3V 8-bit 150MS/s Dual-Channel Time-Interleaved Pipelined A/D Converter”, Department of Electrical Engineering in National Central University.
[18] Behzad Razavi, “Design of Sample-and-Hold Amplifier for High Speed Low Voltage A/D Converters”, IEEE Custom Integrated Circuit Conference, 1997.
[19] M. Choi, and A.A. Abidi, ”A 6b 1.3GS/s A/D Converter in 0.35um CMOS”, in ISSCC Digest of Technical Papers, Feb 2001.
[20] Y.I. Park, S. Karthikenyan, F. Tsay, and E. Bartolome, ”A 10-bit 100MS/s CMOS Pipelined ADC with 1.8V Power Supply,” in ISSCC Digest of Technical Papers, Feb 2001.
[21] L. Sumanen, M. Waltari, and K. Halonen, “A 10-bit 200MS/s CMOS parallel pipelined A/D converter,” IEEE J. of Solid-state Circuits, vol. 36, no. 2, pp. 1048-1055, July 2001.
[22] D. Kelly, Will Yang, Iuri Mehr, Mark Sayuk, Larry Singer, “A 3V 14b 75MS/s CMOS ADC with 85dB SFDR at Nyquist”, in ISSCC Digest of Technical Papers, Feb 2001.
[23] M. Waltari, and K. Halonen, “A 10-BIT 220MS/s CMOS SAMPLE-AND-HOLD CIRCIUT”, IEEE Conference, 1998.
[24] M. Waltari, and K. Halonen, “TIMING SKEW INSENSITIVE SWITCHING FOR DOUBLING-SAMPLING CIRCUITS”, in Proc. ISCAS, vol. 2, June 1999, pp. 61-64.
[25] Dr. Band-Sup Song, “Mixed-Signal Integrated Circuit Design Workshop : SECTION (A) CMOS A/D CONVERTER DESIGN”, IEEE Solid-State Circuits Society Taipei Chapter, 2002.
[26] Andrew M. Abo, and Pual R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipelined Analog-to-Digital Converter”, IEEE J. of Solid-state Circuits, vol. 34, no. 5, pp. 599-606, May 1999.
[27] Y.I. Park, S. Karthikenyan, F. Tsay, and E. Bartolome, ”A 10-bit 100MS/s CMOS Pipelined ADC with 1.8V Power Supply,” in ISSCC Digest of Technical Papers, Feb 2001.
[28] Stephen H. Lewis, H. Scott Fettewrman, George F. Gross, R. Ramachandran, and Tt. R. Viswanathan, “A 10-b 20MSs/s Analog-to-Digital Converter”, IEEE J. of Solid-state Circuits, vol. 27, no. 3, pp. 351-358, March 1992.
[29] Dr. Heng-Chih Lin, “Deep Submicron Mixed-Signal Integrated Circuits Design Workshop”, IEEE Solid-State Circuits Society Taipei Chapter, 2002.
[30] Hui Pan, “A 3.3-V 12-b 50MS/s A/D Converter in 0.6μm CMOS with 80-dB SFDR”, PH.D. dissertation in University of California, Los Angeles, 1999.

指導教授

陳巍仁、劉建男
(Wei-Zen Chen、Chien-Nan Liu)

審核日期

2003-7-9

推文