 |
|
|
|
以作者查詢圖書館館藏 、以作者查詢臺灣博碩士 、以作者查詢全國書目 、勘誤回報 、線上人數：27 、訪客IP：18.118.154.79
姓名 鄭凱元(Kai-Yuan Cheng) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 數位有限脈衝響應多速率無乘法之濾波器/降頻器/升頻器設計及其模組產生器
(Multiplierless Multirate FIR Digital Filter / Decimator / Interpolator Module Generator)相關論文 檔案 [Endnote RIS 格式]
[相關文章]
[文章引用]
[完整記錄]
[館藏目錄]
[檢視]
- 本電子論文使用權限為同意立即開放。
- 已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
- 請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。
摘要(中) 在本篇論文中﹐我們實現了一個濾波器模組產生器。使用者能夠藉由此產生器﹐自動設計出高速低複雜度的數位有限脈衝響應多速率濾波器。此產生器利用線性相位濾波器的對稱性架構﹐並運用多級多速率IFIR濾波器的方法﹐以達到低複雜度之目的。此外﹐運用polyphase representation將濾波器分解成多個子濾波器。所產生的濾波器﹐利用CSD乘法器、transposed direct式架構、和CSA以達到高速的要求。為了擁有良好的適應性﹐輸出的程式碼將以可合成的行為階層硬體描述語言撰寫﹐讓合成工具軟體能依據使用者所指定的條件選擇最適合的架構。
最後﹐我們提供了一個用於64-QAM基頻解調器的濾波器設計實例。使用Synopsys的合成工具並採用TSMC 0.25μm製程設計晶片。結果在低複雜度應用方面﹐減少了32%的面積﹐並節省下44%的功率消耗。而對於高速應用方面﹐此晶片能操作在680 MHz。除此之外﹐還有兩個以此模組產生器設計多階多速率濾波器的例子。摘要(英) A module generator, which can automate the process of designing high-speed low-complexity multirate FIR digital filters, is presented. The generator exploit architectural symmetries in linear phase filters and multistage multirate interpolated FIR filter design methodology for low complexity. In addition, the polyphase representation is used to decompose the filter into subfilters. The resulting filters utilize canonic signed digit (CSD) multipliers, a transposed direct form structure, and carry-save addition for high speed. The generator is designed for maximum flexibility that the output codes are written in a synthesizable behavioral level hardware description language (HDL), which allows the synthesis tool to select the appropriate architecture from user’s constraints.
Finally, a filter design example for 64-QAM baseband demodulator is given. The chip is deigned with TSMC 0.25um process by using the synthesis tool of Synopsys. The area is reduced by 32 percent and the power dissipation is saved by 44 percent for low-complexity applications. Moreover, for high-speed application, the chip can operate at 680 MHz throughput rate. In addition, results of two multistage multirate examples designed with the module generator are also presented.關鍵字(中) ★ 模組產生器
★ 合成器
★ 矽智產
★ 低功率
★ 濾波器
★ 多級多速率
★關鍵字(英) ★ CSD
★ interpolator
★ IFIR
★ polyphase
★ multiplierless
★ decimator
★ filter
★ SIP
★ multistage
★ multirate
★ module generator
★ synthesizer
★ low power論文目次 Chapter 1 Introduction
1.1 Introduction.........................................................................................1
1.2 Motivation...........................................................................................3
1.3 Thesis Organization ............................................................................4
Chapter 2 FIR Digital Filter Design
2.1 Basic FIR Filter Structures .................................................................6
2.1.1 Direct Form Structure ......................................................................7
2.1.2 Transposed Direct Form Structure...................................................9
2.1.3 Carry Save Addition ......................................................................10
2.1.4 Linear Phase FIR Filters ................................................................12
2.2 Multiplierless Filter Design ..............................................................14
2.2.1 CSD Representation.......................................................................14
2.2.2 CSD Multipliers.............................................................................17
2.3 Pipelining..........................................................................................19
2.4 Sign Extension Elimination ..............................................................21
Chapter 3 Multirate FIR Digital Filter Design
3.1 Basic Multirate Operations ...............................................................24
3.1.1 Decimation.....................................................................................24
3.1.2 Interpolation...................................................................................27
3.2 The Noble Identities .........................................................................30
3.3 The Polyphase Representation..........................................................31
3.3.1 Structures for Decimator and Interpolator .....................................33
3.4 Interpolated FIR Filter Design..........................................................38
3.5 Multistage Multirate Filter Design ...................................................40
Chapter 4 Module Generator Implementation
4.1 System Specifications.......................................................................43
4.2 Multistage Architecture Analysis......................................................45
4.3 Coefficient Calculation .....................................................................47
4.4 Coefficient Optimization ..................................................................47
4.4.1 Scaling Strategy.............................................................................49
4.4.2 Local Search Strategy....................................................................51
4.4.3 Overflow Prevention......................................................................52
4.5 Word Length Estimation...................................................................53
4.6 Hardware Estimation ........................................................................55
4.6.1 Hardware Estimation for Single-Stage Design..............................55
4.6.2 Hardware Estimation for Multistage Design .................................55
4.7 Synthesizable Verilog Code Generation ...........................................56
Chapter 5 Experimental Results
5.1 Lowpass Filter ..................................................................................58
5.2 Interpolator .......................................................................................64
5.3 Decimator .........................................................................................65
Chapter 6 Conclusions
References參考文獻 [1] P. P. Vaidyanathan, “Multirate systems and filter banks,” Englewood Cliffs, NJ: Prentice Hall, 1993.
[2] R. E. Crochiere and L. R. Rabiner, “Multirate Digital Signal Processing,” Englewood Cliffs, NJ: Prentice Hall, 1983.
[3] G. W. Reitwiesner, “Binary arithmetic,” Advances in Computers, vol. 1, NY: Academic, pp. 231-308, 1966.
[4] Y. Neuvo, C. Y. Dong, and S. K. Mitra, “Interpolated finite impulse response filters,” IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-32, pp. 563-570, June 1984.
[5] N. J. Fliege, “Multirate digital signal processing: multirate systems, filter banks, wavelets,” 1994.
[6] P. Reutz, “The architectures and design of a 20-MHz real-time DSP chip set,” IEEE JSSC, vol. 24, pp. 338-348, April 1989.
[7] S.-Y. Wu, “Low-power multirate IF digital frequency down converter for wireless communication systems,” MS thesis, Dept. of EE, National Central Univ., Taiwan, June 1997.
[8] R. Hartley, “Subexpression sharing in filters using canonic signed digit multipliers,” IEEE Trans. Circuits Syst. II, vol. 43, pp. 677-688, Oct. 1996.
[9] H. Samueli, “An improved search algorithm for the design of multiplierless FIR filters with powers-of-two coefficients,” IEEE Trans. Circuits Syst., vol. 36, pp. 1044-1047, July 1989.
[10] T.-J. Lin and H. Samueli, “A 200-Mhz CMOS x/sin(x) digital filter for compensating D/A converter frequency response distortion in high-speed communication systems,” IEEE GLOBECOM, vol 3, pp. 1722-1726, Dec. 1990.
[11] R. Jain, P. T. Yang, and T. Yoshino, “FIRGEN: a computer-aided design system for high performance FIR filter integrated circuits,” IEEE Trans. Signal Processing, vol. 39, pp. 1655-1668, July 1991.
[12] R. Hawley, T.-J. Lin, and H. Samueli, “A silicon compiler for high-speed CMOS multirate FIR digital filters,” IEEE Int. Symp. Circuits Syst., vol. 3, pp. 1348-1351, May 1992.
[13] R. A. Hawley, B. C. Wong, T.-J. Lin, J. Laskowski, and H. Samueli, “Design techniques for silicon compiler implementations of high-speed FIR digital filters,” IEEE JSSC, vol. 31, pp. 656-667, May 1996.
[14] I.-C. Park and H.-J. Kang, “Digital filter synthesis based on an algorithm to generate all minimal signed digit representations,” IEEE Trans., CAD of IC and Syst., vol. 21, pp. 1525-1529, Dec. 2002.
[15] A. P. Vinod, E. M.-K. Lai, A. B. Premkumar, and C. T. Lau, “FIR filter implementation by efficient sharing of horizontal and vertical common subexpressions,” Electronics Letters, vol. 39, pp. 251-253, Jan. 2003.
[16] B. C. Wong and H. Samueli, “A 200-MHz all-digital QAM modulator and demodulator in 1.2μm CMOS for digital radio applications,” IEEE JSSC, vol. 26, pp. 1970-1979, Dec. 1991.
[17] M. Bellanger, G. Bonnerot, and M. Coudreuse, “Digital filtering by polyphase network: application to sample rate alteration and filter banks,” IEEE Trans. ASSAP, vol. ASSP-24, pp. 109-114, April 1976.
[18] D. J. Shpak and A. Antoniou, “A generalized Reméz method for the design of FIR digital filters,” IEEE Trans. Circuits Syst., pp. 161-174, Feb. 1990.
[19] C.-L. Chen, K.-Y. Khoo, and A. N. Willson, “An improved polynomial-time algorithm for designing digital filters with power-of-two coefficients,” IEEE Int. Symp. Circuits Syst., vol. 1, pp. 223-226, May 1995.
[20] X. Hu, L. S. DeBrunner, and V. DeBrunner, “An efficient design for FIR filters with variable precision,” IEEE Int. Symp. Circuits Syst., vol. 4, pp. IV-365-IV-368, May 2002.
[21] D. Kodek and K. Steiglitz, “Comparison of optimal and local search methods for designing finite wordlength FIR digital filters,” IEEE Trans, Circuits Syst., vol. 28, pp. 28-32, Jan. 1981.
[22] E. C. Ifeachor and B. W. Jervis, “Digital signal processing: a practical approach,” Addison-Wesley, 1993.
[23] “DesignWare foundation library databook,” Synopsys Inc., Jan. 2002.
[24] C.-L. Chen, “FIR architecture synthesizer based on CSD code,” MS thesis, Dept. of EE, National Central Univ., Taiwan, June 1998.
[25] “The CDMA network engineering handbook, volume 1: concepts in CDMA,” Qualcomm Inc., March 1993.
[26] S.-J. Jou, S.-Y. Wu, and C.-K. Wang, “Low-power multirate architecture for IF digital frequency down converter,” IEEE Trans. Circuits Syst. II, vol. 45, pp. 1487-1494, Nov. 1998.指導教授 周世傑(Shyh-Jye Jou) 審核日期 2003-7-16 推文 plurk
funp
live
udn
HD
myshare
netvibes
friend
youpush
delicious
baidu
網路書籤 Google bookmarks
del.icio.us
hemidemi
facebook
twitter
google
reddit