具資料速率偵測機制之 3~8 Gbps 頻寬可調自適應等化器

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姓名

徐伃葶(Yu-Ting Syu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具資料速率偵測機制之 3~8 Gbps 頻寬可調自適應等化器
(A 3 ~ 8 Gbps Adjustable Bandwidth Adaptive Equalizer With Data Rate Detection Mechanism)

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至系統瀏覽論文 (2027-7-31以後開放)

摘要(中)

近年來隨著製程發展日益精進，資料傳輸量越來越大且資料傳輸速率日漸提升，促使高速串列傳輸介面不斷推陳出新，而舊的傳輸介面仍存在市場上且持續流通。為了使新舊傳輸介面能夠相容，本論文設計一具資料速率偵測機制可操作於 3~8 Gbps 的頻寬可調變自適應等化器，使其能應用於 PCIe 3.0 以及 USB 3.0 的傳輸介面。
由於電路的操作速率為一範圍，若是利用時脈與資料回復電路 (Clock and Data Recovery Circuit, CDR)來進行資料速率的判斷，則電路功耗勢必會上升。考量電路的功耗以及面積成本，所以提出了資料速率偵測機制對資料速率進行判斷，判斷完成後會對等化器的頻寬進行調整，使調頻後的等化器有利於補償更多的通道損失。在資料速率偵測機制方面，為了減少 PVT 變異對資料速率判斷時的影響，加入 PVT 偵測電路對資料速率偵測機制進行校正。

摘要(英)

In recent years, with advances in processes, data transfer volumes have increased significantly and transmission speeds have continued to rise. This trend has driven continuous innovation in high-speed serial transmission interfaces, while older interfaces still remain in the market and circulate. To enable compatibility between new and old transmission interfaces, this thesis designs a bandwidth-adjustable adaptive equalizer with a data rate detection mechanism capable of operating in the range of 3 to 8 Gbps. This allows its application in transmission interfaces such as PCIe 3.0 and USB 3.0.

Due to the operational rate variability of circuits, using a Clock and Data Recovery Circuit (CDR) for data rate determination inevitably increases circuit power consumption. Considering power and area costs, a data rate detection mechanism is presented to detect data rates. Upon detection, the bandwidth of the equalizer will be adjusted, enhancing its capability to compensate for more channel losses. To mitigate the impact of PVT variations on data rate determination, a PVT detection circuit is integrated to calibrate the data rate detection mechanism.

關鍵字(中)

★ 等化器
★ 資料速率偵測機制
★ 寬操作速率

關鍵字(英)

★ Equalizer
★ Data Rate Detector
★ Wide data rate

論文目次

摘要 i
Abstract ii
誌謝 iii
目錄 iv
圖目錄 viiii
表目錄 xi
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 3
第2章高速串列傳輸之訊號完整性 4
2.1 隨機二位元資料 4
2.1.1 機二位元資料特性 4
2.2 傳輸線理論 5
2.2.1 導體損失 8
2.2.2 介質損失 9
2.3 抖動分析 10
2.3.1 隨機抖動(Random Jitter, RJ) 11
2.3.2 定量性抖動(Deterministic Jitter, DJ) 11
2.3.2.1 週期性抖動(Period Jitter, PJ) 12
2.3.2.2 責任週期失真(Duty Cycle Distortion, DCD) 12
2.3.2.3 資料相關抖動(Data Dependent Jitter, DDJ) 13
2.4 單一位元脈衝響應 14
2.5 眼圖分析 16
2.6 誤碼率 17
第3章等化器之背景簡介 20
3.1 等化器的種類 20
3.1.1 連續時間線性等化器 (CTLE) 21
3.1.2 決策回授等化器(DFE) 24
3.1.3 前饋式回授等化器(FFE) 26
3.2 文獻探討 27
3.2.1 應用於寬資料速率的自適應等化器 27
( CTLE + FIR DFE + IIR DFE ) 27
3.2.2 應用於寬資料速率的自適應等化器( CTLE + FIR DFE ) 28
3.2.3 應用於寬資料速率的自適應等化器 ( CTLE ) 29
3.3 比較與討論 30
第4章自適應等化器架構設計與實現 31
4.1 電路架構 31
4.2 電路操作簡介 32
4.2.1 資料速率偵測機制 32
4.2.2 資料邊緣計數自適應機制 33
4.3 行為模擬 34
4.4 子電路介紹 38
4.4.1 連續時間線性等化器(CTLE) 38
4.4.2 擺幅轉換電路(CML to CMOS Converter)[32] 40
4.4.3 資料速率偵測器(Data Rate Detector) 41
4.4.4 資料邊緣計數自適應機制 44
4.4.5 鎖定關閉電路 47
4.5 模擬結果 48
4.5.1 通道模型 48
4.5.2 佈局前模擬 52
4.5.2.1 資料速率@ 8 Gbps 52
4.5.2.2資料速率@ 6 Gbps 54
4.5.2.3資料速率@ 3Gbps 55
4.5.3 佈局後模擬 56
4.5.3.1 資料速率@ 8Gbps 56
4.5.3.2 資料速率@ 6Gbps 58
4.5.3.3資料速率@ 3Gbps 60
4.5.4 模擬結果統整 63
第5章晶片佈局與量測 67
5.1 電路佈局 67
5.1.1 佈局規劃與電源規劃 68
5.2 量測考量 69
5.2.1 量測環境考 69
5.2.2 高速輸入緩衝器 70
5.2.3 高速輸出緩衝器 71
5.3 規格比較表 72
第6章結論 73
6.1 結論 73
參考文獻 74

參考文獻

[1]孫世洋, “以符碼間干擾偵測技術實現自適應等化器之 5 Gbps 半速率時脈與資料回復電路,” 碩士論文, 國立中央大學, 2016.
[2]VESA DisplayPort Standard, Version 2.0, Jun. 2019.
[3]Universal Serial Bus Specification, Revision 3.1, USB-IO, 2013.
[4]Serial ATA Specification, Revision 3.5a, SATA-IO, Mar. 2021.
[5]PCI Express Base Specification, Revision 6.0, Version 1.0, PCI-SIG, Jan. 2022.
[6]B. Razavi, “Basic concepts,” in Design of Integrated Circuits for Optical Communications, 1st ed. New York, NY, USA: McGraw-Hil]l, 2003, ch. 2, sec. 1, pp. 8-11.
[7]F. T. Ulaby and U. Ravaioli, “Transmission Lines,” in Fundamentals of Applied Electromagnetics, 6th ed. United Kingdom: Pearson, 2015, ch. 2, pp. 62-134.
[8]S. H. Hall, G. W. Hall, and J. A. McCall, High-speed digital system design-Ahandbook of interconnect theory and design practices, John-Wiley, 1st ed., 2002.
[9]J. C. Rautio and V. Demir, "Microstrip conductor loss models for electromagnetic analysis," in IEEE Transactions on Microwave Theory and Techniques, vol. 51, no. 3, pp. 915-921, March 2003.
[10]Tektronix, “數位示波器的應用抖動(jitter)測量”.
[11]Tektronix, “ 時序水平抖動的認識和特性分析 ”. Available: https://www.tek.com/tw/solutions/application/jitter-measurement-and-timing analysis.
[12]B. Razavi, “Noise,” in Design of Analog CMOS Integrated Circuits, 2nd ed. New York, NY, USA: McGraw-Hill, 2017, ch. 7, pp. 201-239.
[13]R. Sarpeshkar, T. Delbruck and C. A. Mead, “White noise in MOS transistors and resistors,” IEEE Circuits and Devices Magazine, vol. 9, no. 6, pp. 23-29, Nov. 1993.
[14]Agilent Technologies, “Jitter Fundamentals: Agilent 81250 ParBERT Jitter Injection and Analysis Capabilities,” Application Note: 5988-9756EN, July 17, 2003.
[15]N. Radhakrishnan, B. Achkir, J. Fan and J. L. Drewniak, “Stressed jitter analysis for physical link characterization,” in Proc. IEEE International Symposium on Electromagnetic Compatibility, Feb. 2010, pp. 568-572.
[16]Agilent Technologies, “Finding sources of jitter with real-time jitter analysis,” 2008.
[17]Y. Wu, “An improved statistical analysis method for duty cycle distortion jitter analysis,” in Proc. IEEE International Symposium on Consumer Electronics (ISCE), Jun. 2013, pp. 31-32.
[18]N. Na, D. M. Dreps and J. A. Hejase, “DC wander effect of DC blocking capacitors on PCIe Gen3 signal integrity,” in Proc. IEEE 63rd Electronic Components and Technology Conference, May 2013, pp. 2063-2068.
[19]黃清和, “具可補償 19-40 dB 通道衰減之 20 Gbps 接收端自適應等化器,” 碩士論文, 國立中央大學, 2022.
[20]Altera Corporation, “Deterministic Jitter (DJ) Definition and Measurement,” 2009.
[21]Maxim, “Optical receiver performance evaluation”.
[22]Kuo-Hsing Cheng, Yu-Chang Tsai, Yen-Hsueh Wu, and Ying-Fu Lin,“A 5-Gb/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications ,” IEEE Trans. Circuits Syst. II, Express Briefs , vol. 57 , no. 5 , pp. 324-328 , May. 2010
[23]Jun Won Jung, and Behzad Razavi, “A 25 Gb/s 5.8 mW CMOS Equalizer,” IEEE J. Solid-State Circuits, vol. 50, no. 2, pp. 515–526, Feb. 2015.
[24]Jri Lee, Ping-Chuan Chiang, Pen-Jui Peng, Li-Yang Chen, and Chih-Chi Weng, “Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies,” IEEE J. Solid-State Circuits, vol. 50, no. 9, pp. 2061–2072, Sep. 2015.
[25]T. Wang et al., "A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process," in IEEE Journal of Solid-State Circuits, vol. 57, no. 8, pp. 2521-2531, Aug. 2022
[26]A. Aghighi, A. Tajalli and M. Taherzadeh-Sani, "A Low-Power 10 to 15 Gb/s Common-Gate CTLE Based on Optimized Active Inductors," 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC), Salt Lake City, UT, USA, 2020, pp. 171-175.
[27]K. -Y. Chen, W. -Y. Chen and S. -I. Liu, “A 0.31-pJ/bit 20-Gb/s DFE with 1 discrete tap and 2 IIR filters feedback in 40-nm-LP CMOS,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 64, no. 11, pp. 1282-1286, Nov. 2017.
[28]J.-S Choi, M.-S Hwang, and D.-K. Jeong, “A 0.18-µm CMOS 3.5-Gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method,” IEEE J.Solid-State Circuits, vol. 39, no. 3, pp.419-425, Mar. 2004.

[29]K. Park et al., "A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 12, pp. 1432-1436, Dec. 2017.
[30]J. Lee, K. Lee, H. Kim, B. Kim, K. Park and D. -K. Jeong, "A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference," in IEEE Journal of Solid-State Circuits, vol. 55, no. 8, pp. 2186-2195, Aug. 2020.
[31]S. Choi et al., "A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 2, pp. 276-287, Feb. 2016.
[32]Y. -F. Lin, C. -C. Huang, J. -Y. M. Lee, C. -T. Chang and S. -I. Liu, "A 5–20 Gb/s power scalable adaptive linear equalizer using edge counting," 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), KaoHsiung, Taiwan, 2014.
[33]R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara, "1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS," IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 53, pp. 220-224, Mar. 2006.
[34]李曼如, “具可關閉數位控制式自我斜率偵測機制之低功率適應性等化器,” 碩士論文,國立中央大學, 2015.
[35]Keysight, “M8048A ISI Channels - Data Sheet”.
[36]Y. -H. Tu, K. -H. Cheng, M. -J. Lee and J. -C. Liu, "A Power-Saving Adaptive Equalizer With a Digital-Controlled Self-Slope Detection," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 7, pp. 2097-2108, July 2018.
[37]S. Hwang, J. Song, Y. Lee and C. Kim, "A 1.62–5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 10, pp. 2691-2702, Oct. 2017.
[38]Z. Shu et al., "A 5–13.5 Gb/s Multistandard Receiver With High Jitter Tolerance Digital CDR in 40-nm CMOS Process," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 10, pp. 3378-3388, Oct. 2020.
[39]C. -C. Wang, K. -Y. Chao, S. Sampath and P. Suresh, "Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 9, pp. 2069-2073, Sept. 2020.
[40]D. Wang, Y. Zhao, Q. Yao, Y. Cao, B. Lian and H. Zhang, "Electrical simulation of gold bonding wire with different parameters," 2015 16th International Conference on Electronic Packaging Technology (ICEPT), Changsha, China, 2015, pp. 1329-1333
[41]C. -C. Wang, K. -Y. Chao, S. Sampath and P. Suresh, "Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 9, pp. 2069-2073, Sept. 2020

指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2024-7-26

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