使用 90-nm CMOS 與 100-nm GaAs pHEMT 製程之 Q 頻段與 E 頻段功率放大器

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姓名

劉鎮潁(Jen-Ying Liu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

使用 90-nm CMOS 與 100-nm GaAs pHEMT 製程之 Q 頻段與 E 頻段功率放大器
(Q-band and E-band Power Amplifiers in 90-nm CMOS and 100-nm GaAs pHEMT Technologies)

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至系統瀏覽論文 (2027-8-7以後開放)

摘要(中)

本論文主要聚焦於功率放大器的設計與討論，我們分別使用了 TSMC 90-nm CMOS 製程和 WIN 100-nm GaAs pHEMT 製程來實現各種不同架構的功率放大器。

在第二章，我們接續實驗室學長的電路，並重新設計一使用 TSMC 90-nm CMOS 製程並操作於 Q 頻段中心頻率 40 GHz 之功率放大器。本電路為一差動電路，在輸入及輸出端使用變壓器來進行匹配，同時使訊號進行單端與雙端的轉換。我們使用中和電容技術來達到最佳的穩定效果與最大可用增益，且使用 Cascode 架構使操作電壓提高，以此來提升輸出功率。小訊號量測結果與模擬結果整體非常接近，而大訊號量測結果在操作頻率 40 GHz下，OP1dB 為12.9 dBm，在 P1dB 下的 PAE 為 7.28%。

在第三章，我們設計一使用 WIN 100-nm GaAs pHEMT 製程並操作於 Q 頻段中心頻率為 40 GHz之功率放大器，其架構為二級平衡式功率放大器，並使用 Lange coupler 來實現二路功率合併。我們參考了之前的下線結果，該結果為兩個單級功率放大器，這兩個單級功率放大器電晶體尺寸分別與本章電路驅動級和輸出級相同。透過對這兩個單級功率放大器進行偵錯與重新模擬，並將此結果應用於本章電路設計。量測結果在操作頻率 40 GHz 下增益約為 13.4dB，OP1dB 為 27.8 dBm，在 P1dB 下的 PAE 結果為 27.7%。

在第四章，我們設計一使用 WIN 100-nm GaAs pHEMT 製程並操作於 E 頻段中心頻率為 80 GHz之功率放大器，其架構為三級放大器。我們參考了之前的下線的一單級功率放大器，此單級功率放大器電晶體尺寸與本章電路第二和第三級相同。透過對此單級功率放大器進行偵錯與重新模擬，並將此結果應用於本章電路設計。量測結果在操作頻率 80GHz 下增益約為 12.4 dB，OP1dB 為 22.7 dBm，在 P1dB 下 PAE 為 29.4%。

摘要(英)

This thesis mainly focuses on the design and analysis of power amplifiers. We use the TSMC 90-nm CMOS process and WIN 100-nm GaAs pHEMT process to implement various power amplifier architectures.

In Chapter 2, we continue the work of previous lab members and redesign a power amplifier using the TSMC 90-nm CMOS process, operating at a center frequency of 40 GHz in the Q-Band. This circuit is a differential architecture, using transformers at the input and output for matching, and to achieve single-ended to differential signal conversion. We used neutralization capacitor technology to achieve optimal stability and maximum available gain, and employed a cascode architecture to increase the operating voltage, thereby enhancing the output power. The small-signal measurement results closely match the simulation results, and the large-signal measurement results at the operating frequency of 40 GHz show the OP1dB is 12.9 dBm and the PAE is 7.28% at P1dB.

In Chapter 3, we design a power amplifier using the WIN 100-nm GaAs pHEMT process, operating at a center frequency of 40 GHz in the Q-Band. This power amplifier has a two-stage balanced architecture and uses a Lange coupler for power combining. We referenced previous results, which were for two single-stage power amplifiers with transistor sizes corresponding to the driver and output stages of the circuit in this chapter. Through debugging and re-simulating these two single-stage power amplifiers, we applied the findings to the design in this chapter. The measurement results show a gain of approximately 13.4 dB, OP1dB is 27.8 dBm, and the PAE is 27.7% at P1dB, measured at 40 GHz.

In Chapter 4, we design a power amplifier using the WIN 100-nm GaAs pHEMT process, operating at a center frequency of 80 GHz in the E-Band. This amplifier has a three-stage architecture. We referenced a previously fabricated single-stage power amplifier with transistor sizes corresponding to the second and third stages of the circuit in this chapter. Through debugging and re-simulating this single-stage power amplifier, we applied the findings to the design in this chapter. The measurement results show a gain of approximately 12.4 dB, OP1dB is 22.7 dBm, and the PAE is 29.4% at P1dB, measured at 80 GHz.

關鍵字(中)

★ 功率放大器
★ Q 頻段
★ E 頻段
★ 砷化鎵

關鍵字(英)

★ Power Amplifier
★ Q-band
★ E-band
★ GaAs
★ CMOS

論文目次

摘要. . . I
Abstract . . . III
目錄. . . V
圖目錄. . . VII
表目錄. . . XI
第一章緒論. . . 1
1.1研究動機與背景. . . 1
1.2論文架構. . . 2
第二章Q頻段使用中和電容技術CMOS功率放大器. . . 3
2.1簡介. . . 3
2.2電路設計. . . 4
2.2.1先前下線結果之電路偵錯與重新模擬. . . 4
2.2.2電容中和技術. . . 8
2.2.3電路重新設計. . . 10
2.3電路模擬與量測. . . 16
2.3.1模擬結果. . . 16
2.3.2量測結果. . . 21
2.4結果與討論. . . 24
第三章Q頻段砷化鎵二級平衡式功率放大器. . . 27
3.1簡介. . . 27
3.2電路設計. . . 28
3.2.1電晶體尺寸及偏壓選擇. . . 28
3.2.2先前下線結果之電路偵錯與重新模擬. . . 32
3.2.3整體電路設計概述. . . 41
3.3電路模擬與量測. . . 48
3.3.1電路模擬. . . 48
3.3.2量測結果. . . 55
3.4電路偵錯與重新模擬. . . 62
3.5結果與討論. . . 64
第四章E頻段砷化鎵三級功率放大器. . . 67
4.1簡介. . . 67
4.2電路設計. . . 68
4.2.1電晶體尺寸及偏壓選擇. . . 68
4.2.2先前下線結果之電路偵錯與重新模擬. . . 71
4.2.3整體電路設計概述. . . 75
4.3電路模擬與量測. . . 79
4.3.1電路模擬. . . 79
4.3.2量測結果. . . 83
4.4電路偵錯與重新模擬. . . 87
4.5結果與討論. . . 88
第五章結論. . . 91
參考文獻. . . 93

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指導教授

傅家相(Jia-Shiang Fu)

審核日期

2024-8-14

推文