使用 90-nm CMOS 與 100-nm GaAs pHEMT 製程之 Q 頻段與 E 頻段低雜訊放大器

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江易紘(Yi-Hung Chiang) 查詢紙本館藏

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電機工程學系

論文名稱

使用 90-nm CMOS 與 100-nm GaAs pHEMT 製程之 Q 頻段與 E 頻段低雜訊放大器
(Q-band and E-band Low-Noise Amplifiers in 90-nm CMOS and 100-nm GaAs pHEMT Technologies)

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至系統瀏覽論文 (2027-8-7以後開放)

摘要(中)

在本論文中，我們採用了 90-nm CMOS 製程設計了 Q 頻段的低
雜訊放大器，以及使用 WIN 100-nm GaAs pHEMT 製程實現了 E 頻
段的低雜訊放大器。
在第一章中，我們闡述研究動機與背景，由於高資料傳輸率的移
動通訊系統應用需求增加，以及較低頻率商用頻段的飽和，使得毫
米波頻段成為近年來的一個發展重點。 Q 頻段之應用，包括氣象雷
達、第五代行動通訊，以及新興的衛星網際網路，如 Starlink。根據
3GPP 的規範，第五代行動通訊 frequency range 2 （FR2）中的 n260
及 n259 頻段分別為 3740 GHz 及 39.543.5 GHz，如衛星網際網路
的 downlink 就是使用 37.542 GHz，而 uplink 是使用 47.250.2 GHz
及 50.451.4 GHz。E 頻段之應用，包括對等式網路（P2P）7176
GHz 、 8186 GHz 和汽車長距雷達（7677 GHz）與短距雷達（7781
GHz）等應用。低雜訊放大器身為接收鏈第一級放大的元件，在通
訊系統中，接收機的靈敏度取決於整體的雜訊指數（noise gure,
NF），雜訊指數越低代表對抗雜訊的能力越強、對訊號的靈敏度越
高。依據雜訊指數的串接公式（Friis′ formula），後級的雜訊會被前
級的增益所抑制，而低雜訊放大器身為接收端第一級提供訊號放大的
電路，其性能對於整體系統絕對是至關重要。
在第二章中，我們使用 90-nm CMOS 製程設計了一個操作中心
頻率為 40 GHz 的 Q 頻段低雜訊放大器。在傳統的收發機會有一個開
關在前端進行切換 TX mode 與 RX mode，此開關位於 PA 的後端及
LNA 的前端，開關所造成的損耗會對於整體收發機系統會有極大的影
響。為了減少開關所造成的損耗，我們提出將開關融入 LNA 電路之
中。此方法不需要一個額外的開關來控制系統，便可以達成減少整體
系統損耗之目的。在 40 GHz 中心頻率下，該放大器量測結果有 6.46
dB 的增益，且返回損耗均大於 8 dB，在40 GHz 下的單端輸出 NF
為 5.73 dB， IP1dB 約為 −2.5 dBm。量測結果在 32 GHz 附近 on o
ratio 仍然有 18 dB，這代表我們設計的開關在 on o 狀態之間還是有
良好的區隔，有達到此電路設計之目的。
在第三章中，我們使用 WIN 100-nm GaAs pHEMT 製程提出了
一個 Q 頻段二級低雜訊放大器設計，吸收了先前下線的經驗進行優
化。該電路同樣以 40 GHz 為中心頻率。這個設計採用了二級 Cascode
架構，第一級採用 Cascode，第二級則為 Common-Source （CS）。
在 40 GHz 操作頻率下，小信號量測增益為 26.5 dB。雜訊量測範圍
涵蓋 37 至 50 GHz，且 40 GHz 的 NF 為 2.21 dB，IP1dB 達 −18.8
dBm。此電路在 Q 頻段下取得不錯的綜合效能。與 CMOS 和 SiGe
製程相比在 NF 及 gain 上具有優勢，但在功耗上較高。與 GaN 相比
在 NF 和 gain 表現大致相同，在功耗上具有優勢。
在第四章中，我們我們使用 WIN 100-nm GaAs pHEMT 製程設
計了一個適用於 E 頻段的二級低雜訊放大器。該電路第一級為 CS，
第二級為 Cascode。在 80 GHz 操作頻率下，該放大器達到 21.8 dB
的增益。雜訊量測範圍涵蓋 75 至 90 GHz，且 80 GHz 的 NF 為 4.5
dB，IP1dB 達 −18 dBm。此電路在 E 頻段下取得不錯的效能，與其
他製程相比在 gain 上具有優勢， NF 及功率消耗上效能尚可，無明顯
短板。本電路在優化方面仍有相當大的潛力，透過選用較小的穩定電
阻，預估能夠進一步提升性能。
最後，在第五章中，我們總結了本論文所使用 90-nm CMOS 製程
及 WIN 100-nm GaAs pHEMT 製程設計之 Q 頻段與 E 頻段低雜訊放
大器。使用 90-nm CMOS 製程之 Q 頻段低雜訊放大器量測結果在 32
GHz 附近 on o ratio 仍然有 18 dB，這代表我們設計的開關在 on o
狀態之間還是有良好的區隔，有達到此電路設計之目的:為了減少開關
所造成的所耗，將開關融入 LNA 電路之中。使用 WIN 100-nm GaAs
pHEMT 製程之 Q 頻段低雜訊放大器在 40 GHz 頻段下與其他製程
相比在 NF 及 gain 表現上具有優勢或相當。使用 WIN 100-nm GaAs
pHEMT 製程之 E 頻段低雜訊放大器在 80 GHz 頻段下取得不錯的綜
合效能，與其他製程相比在 gain 上具有優勢， NF 及功率消耗上效能
尚可，無明顯短板。

摘要(英)

In this paper, we designed a Q-Band low-noise amplier (LNA)
using a 90-nm CMOS process and realized an E-Band LNA using the WIN 100-nm GaAs pHEMT process.
In Chapter 1, we elaborate on the research motivation and background. With the increasing demand for high-data-rate mobile communication systems and the saturation of Lower-Frequency commercial bands, Millimeter-Wave frequencies have become a focal point of recent developments. Q-Band applications include weather radar, fthgeneration mobile communications, and emerging satellite internet services such as Starlink. According to 3GPP specications , the FifthGeneration mobile communication frequency range 2 (FR2) bands n260
and n259 are 3740 GHz and 39.543.5 GHz, respectively. Satellite internet downlink uses 37.5-42 GHz, while uplink uses 47.250.2 GHz and
50.451.4 GHz. E-Band applications include Point-to-Point networks
(P2P) at 7176 GHz, 81-86 GHz, and automotive Long-Range radar
(7677 GHz) and Short-Range radar (7781 GHz). As the rst stage
of amplication in the receiver chain, the LNA is crucial for communication systems, where the receiver′s sensitivity depends on the overall
noise gure (NF). A lower noise gure indicates better noise immunity
and higher signal sensitivity. According to the Friis′ formula, the noise
of subsequent stages is suppressed by the gain of the preceding stages,
making the LNA′s performance critical for the overall system.
In Chapter 2, we designed a Q-Band LNA with a center frequency of 40 GHz using a 90-nm CMOS process. Traditionally, a transceiver
switch toggles between TX mode and RX mode at the front end. This
switch, located after the PA and before the LNA, can cause signicant
loss aecting the overall transceiver system. To reduce this loss, we
integrated the switch into the LNA circuit. This approach eliminates
the need for an additional switch, thereby reducing the overall system
loss. At a 40 GHz center frequency, the amplier measured a gain of
6.46 dB, with return losses greater than 8 dB. The single-ended output
NF at 40 GHz was 5.73 dB, and the IP1dB was approximately −2.5
dBm. The On-O ratio near 32 GHz remained 18 dB, indicating that
our switch design maintained good isolation between on and o states,
meeting the design objectives.
In Chapter 3, we proposed a Q-Band two-stage LNA design using
the WIN 100-nm GaAs pHEMT process, incorporating previous tapeout experiences for optimization. This circuit also targets a 40 GHz
center frequency, employing a two-stage Cascode architecture: the rst
stage is a Cascode, and the second stage is a Common-Source (CS). At
40 GHz, the small-signal gain was measured at 26.5 dB. Noise gure
measurements covered the 3750 GHz range, with an NF of 2.21 dB
at 40 GHz, and the IP1dB reached −18.8 dBm. This circuit achieved
good overall performance in the Q-Band, showing advantages in NF
and gain compared to CMOS and SiGe processes, though with higher
power consumption. Compared to GaN, it exhibited similar NF and
gain performance but with a power consumption advantage.
In Chapter 4, we designed an E-Band two-stage LNA using the
WIN 100-nm GaAs pHEMT process. The circuit features a CS rst stage
and a Cascode second stage. At an operating frequency of 80 GHz, the
amplier achieved a gain of 21.8 dB. Noise gure measurements covered
the 7590 GHz range, with an NF of 4.5 dB at 80 GHz, and the IP1dB
reached −18 dBm. This circuit demonstrated good performance in the
E-Band, showing a gain advantage compared to other processes, with
satisfactory NF and power consumption performance and no signicant
shortcomings. There remains considerable potential for optimization;
reducing the stabilizing resistor could potentially enhance performance
further.
Finally, in Chapter 5, we summarize the Q-Band and E-Band LNAs
designed using the 90-nm CMOS and WIN 100-nm GaAs pHEMT processes. The Q-Band LNA using the 90-nm CMOS process showed an
On-O ratio of 18 dB near 32 GHz, indicating good isolation between
on and o states, meeting the design objective of integrating the switch
into the LNA to reduce system loss. The Q-Band LNA using the WIN
100-nm GaAs pHEMT process demonstrated advantages or comparable
performance in NF and gain at 40 GHz compared to other processes.
The E-Band LNA using the WIN 100-nm100-nm GaAs pHEMT process
achieved good overall performance at 80 GHz, with a gain advantage,
satisfactory NF, and power consumption, with no signicant shortcomings.

關鍵字(中)

★ 低雜訊放大器
★ Q 頻段
★ E 頻段
★ CMOS
★ GaAs

關鍵字(英)

★ Low-Noise Amplifiers
★ Q-Band
★ E-Band
★ CMOS
★ GaAs

論文目次

摘要. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV
目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VII
圖目錄 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IX
表目錄 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XIII
第一章緒論 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 研究動機與背景 . . . . . . . . . . . . . . . . . . . . 1
1.2 論文架構 . . . . . . . . . . . . . . . . . . . . . . . . 3
第二章 Q 頻段整合開關之低雜訊放大器 . . . . . . . . . . . . 5
2.1 簡介 . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 電路模擬與量測 . . . . . . . . . . . . . . . . . . . . 6
2.2.1 電路設計 . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.2 模擬結果 . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.3 量測結果 . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2.4 電路偵錯與重新模擬 . . . . . . . . . . . . . . . . . . 32
2.3 結果與討論 . . . . . . . . . . . . . . . . . . . . . . . 38
第三章 Q 頻段砷化鎵之二級低雜訊放大器. . . . . . . . . . . 41
3.1 簡介 . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2 電路設計 . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2.1 先前電路偵錯之結果 . . . . . . . . . . . . . . . . . . 42
3.2.2 電晶體尺寸及偏壓選擇 . . . . . . . . . . . . . . . . 47
3.2.3 電路設計 . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3 電路模擬與量測 . . . . . . . . . . . . . . . . . . . . 55
3.3.1 模擬結果 . . . . . . . . . . . . . . . . . . . . . . . . 55
3.3.2 量測結果 . . . . . . . . . . . . . . . . . . . . . . . . 60
3.3.3 電路偵錯與重新模擬 . . . . . . . . . . . . . . . . . . 66
3.4 結果與討論 . . . . . . . . . . . . . . . . . . . . . . . 69
第四章 E 頻段砷化鎵之二級低雜訊放大器. . . . . . . . . . . 71
4.1 簡介 . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.2 電路設計 . . . . . . . . . . . . . . . . . . . . . . . . 72
4.2.1 先前電路偵錯之結果電路偵錯之結果 . . . . . . . . . 72
VII
4.2.2 電路設計 . . . . . . . . . . . . . . . . . . . . . . . . 75
4.3 電路模擬與量測 . . . . . . . . . . . . . . . . . . . . 81
4.3.1 模擬結果 . . . . . . . . . . . . . . . . . . . . . . . . 81
4.3.2 量測結果 . . . . . . . . . . . . . . . . . . . . . . . . 86
4.3.3 電路偵錯與重新模擬 . . . . . . . . . . . . . . . . . . 92
4.4 結果與討論 . . . . . . . . . . . . . . . . . . . . . . . 95
第五章結論 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

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指導教授

傅家相(Jia-Shiang Fu)

審核日期

2024-8-14

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