使用100-nm GaAs pHEMT 與 90-nm CMOS 製程之 Q 頻段功率放大器與全通相位偏移器

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黃紹傑(Shao-Jie Huang) 查詢紙本館藏

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電機工程學系

論文名稱

使用100-nm GaAs pHEMT 與 90-nm CMOS 製程之 Q 頻段功率放大器與全通相位偏移器
(Q-Band Power Amplifiers and All-Pass Phase Shifters in 100-nm GaAs pHEMT and 90-nm CMOS Technologies)

相關論文

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至系統瀏覽論文 (2027-8-14以後開放)

摘要(中)

毫米波頻段中的 Q 頻段（33-50.5 GHz）因其具有較大的頻寬、
更快的傳輸速率以及更短的延遲，近年來被廣泛應用於氣象雷達、第
五代行動通訊（5G）以及新興的衛星網際網路等領域。在這些應用
中，相位陣列和放大器在收發機架構中起著關鍵作用。其中，相位偏
移器在相位陣列中扮演著至關重要的角色，通過提供可調變的相位差
給相位陣列中的天線，來改變相位陣列發射與接收的方向，從而實現
精確的波束控制和靈活的通信操作。
在第二章中。我們使用 TSMC 90-nm CMOS 製程，實現一Q 頻
段全差動式六位元被動式相位偏移器（中心頻設計在38 GHz）。
此電路的數位式相移級和類比式相移級都是使用傳輸線基準全
通網路來實現，兩級透過中心頻率不同的傳輸線基全通網路的
架構串接而成，使電路可以實現寬頻的效果。而 45◦ 以下的相移
量，22.5◦、11.5◦、5.625◦ 則是採類比式的相移器來實現，並搭配 3-bit
的 DPOT（digital potentiometer)，讓類比式相移器透過數位的方式
來控制，由給定的電壓範圍來讓 MOS varactor 組成的類比式相移器
達到我們想要的相移量。雖然類比式相移器的線性度會較差，但能透
過一級的類比式相移器取代三級的數位相移器，來使植入損耗降低，
最後為了實現360◦ 的相移器，所以最後180◦ 的相移量可以採用一對
SPDT（single pole double throw）的開關架構來實現，此架構不僅能
減少電路面積及植入損耗，還能達到寬頻的效果。
在第三章中。為探討 Q 頻段砷化鎵全通網路的相位偏移器的設
計。該電路為使用 WIN 100-nm GaAs pHEMT 製程實現，利用全通
網路的架構，透過傳輸線的方式搭配二極體會隨著電壓變化，而造成的容值變化來達到不同的相移量。此電路將以單級相位偏移器實現
60◦ 的相移量，並串接成 3-stage 的相位偏移器來達到 180◦ 以上的相
移量。
在第四章中。為探討 Q 頻段砷化鎵功率放大器的設計。該電路
採用單級共源放大器的架構，使用這一基本架構的目的是透過此次下
線經驗來測試此製程對電路性能的極限，以及檢驗設計流程和模擬
方法的有效性。此電路是利用 WIN 100-nm GaAs pHEMT 製程實現
的，分別是電晶體尺寸的指狀為 8 finger，UGW (unit gate width) 為
50 μm，而 layout option 為 4n 和 8n 兩種。阻抗匹配採用兩種方式，
一種是為了避免每次製程變異可能帶來的影響，而採用傳輸線來進行
阻抗匹配;一種為了使面積更小而使用集總元件LC 和傳輸線來進行匹
配。此外，我們還採用了 RC 並聯的方式串聯在電晶體的閘極端，以
確保電路在操作頻段內的穩定性；在低頻部分，我們則使用bypass 電
容來穩定電路。
本文探討了毫米波頻段中 Q 頻段（33-50.5 GHz）相位陣列系
統中相位偏移器和放大器的設計。研究中，我們使用 TSMC 90-nm
CMOS 製程和 WIN-100 nm GaAs pHEMT 製程，分別實現了全差動
式六位元被動式相位偏移器和高效能的功率放大器。這些元件在高頻
應用中展現了卓越的性能，有效提高了信號的增益和穩定性。

摘要(英)

The Q-band (33-50.5 GHz) in the millimeter-wave spectrum has
been widely applied in recent years due to its large bandwidth, faster
transmission rates, and lower latency. Applications of the Q-band include
weather radar, fth-generation (5G) mobile communications, and
emerging satellite internet. In these applications, phased arrays and amplifiers play critical roles in transceiver architectures. The phase shifter
is particularly crucial in phased arrays, providing adjustable phase differences
to the antennas within the array, thereby altering the transmission
and reception directions for precise beam control and exible
communication operations.
In Chapter 2, we implemented a fully dierential 6-bit passive phase
shifter for the Q-band (center frequency designed at 38 GHz) using
TSMC 90-nm CMOS technology. Both the analog and digital phase
shifting stages of this circuit are realized using transmission line-based
all-pass networks. These stages are cascaded with dierent center frequencies,
enabling broadband performance. Phase shifts below 45◦, including
22.5◦, 11.5◦, and 5.625◦, are achieved with analog phase shifters,
controlled digitally by a 3-bit digital potentiometer (DPOT). The analog
phase shifter utilizes MOS varactors to achieve the desired phase shift
within a specied voltage range. Despite the poorer linearity of analog
phase shifters, a single-stage analog phase shifter can replace three
stages of digital phase shifters, reducing insertion loss. To achieve 360◦
phase shift, a pair of single-pole double-throw (SPDT) switches is used for the final 180◦ phase shift. This design minimizes circuit area and
insertion loss while maintaining broadband performance.
Chapter 3 explores the design of a Q-band GaAs all-pass network
phase shifter. Implemented using WIN 100-nm GaAs pHEMT technology,
this circuit achieves variable phase shifts through transmission lines
and diodes whose capacitance varies with voltage. A single-stage phase
shifter achieves a 60◦ phase shift, and a 3-stage conguration achieves
phase shifts above 180◦.
In Chapter 4, we investigate the design of a Q-band GaAs power
amplifier. Using a single-stage common-source amplifier architecture,
this circuit aims to test the process limits and validate design and simulation
methodologies through practical implementation. The amplifier,
realized with WIN 100-nm GaAs pHEMT technology, features an 8-
nger transistor with a unit gate width (UGW) of 50 μm and layout
options of 4n and 8n. Impedance matching is achieved through transmission
lines to mitigate process variations and through lumped LC
components and transmission lines to minimize area. Additionally, RC
parallel networks are used at the transistor gates for stability within
the operating frequency band, and bypass capacitors are employed to
stabilize the circuit at low frequencies.
This study explores the design and performance optimization of
phase shifters and amplifiers in Q-band phased array systems using
TSMC 90-nm CMOS and WIN 100-nm GaAs pHEMT technologies.
These components demonstrate excellent performance in high-frequency
applications, eectively enhancing signal gain and stability.

關鍵字(中)

★ 相位偏移器
★ 功率放大器
★ Q頻段
★ CMOS
★ GaAs
★ 全通網路

關鍵字(英)

論文目次

摘要. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III
目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
圖目錄 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VII
表目錄 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XIII
第一章緒論 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 研究動機與背景 . . . . . . . . . . . . . . . . . . . . 1
1.2 論文架構 . . . . . . . . . . . . . . . . . . . . . . . . 2
第二章 Q 頻段全差動式六位元被動式相位偏移器 . . . . . . 3
2.1 簡介 . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 電路設計 . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.1 45◦ 及 90◦ 相位偏移器 . . . . . . . . . . . . . . . . . 7
2.2.2 類比級相位偏移器 . . . . . . . . . . . . . . . . . . . 13
2.2.3 180◦ 相位偏移器 . . . . . . . . . . . . . . . . . . . . 17
2.3 模擬結果 . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4 量測結果 . . . . . . . . . . . . . . . . . . . . . . . . 28
2.5 結論 . . . . . . . . . . . . . . . . . . . . . . . . . . 40
第三章 Q 頻段砷化鎵 3-stage 全通網路的相位偏移器 . . . . 43
3.1 簡介 . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.2 電路設計 . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3 電路模擬與量測 . . . . . . . . . . . . . . . . . . . . 45
3.3.1 模擬結果 . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.2 量測結果 . . . . . . . . . . . . . . . . . . . . . . . . 51
3.4 結果與討論 . . . . . . . . . . . . . . . . . . . . . . . 59
第四章應用於 5G 毫米波頻段的功率放大器. . . . . . . . . . 61
4.1 簡介 . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.2 電路模擬量測與偵測結果 . . . . . . . . . . . . . . . 62
4.3 電路設計 . . . . . . . . . . . . . . . . . . . . . . . . 68
4.3.1 電晶體尺寸及偏壓選擇 . . . . . . . . . . . . . . . . 68
4.3.2 電路設計方式 . . . . . . . . . . . . . . . . . . . . . 71
4.4 電路模擬與量測 . . . . . . . . . . . . . . . . . . . . 77
V
4.4.1 layout option 為 4n 8×50 µm 模擬結果 . . . . . . . 77
4.4.2 layout option 為 4n 8×50 µm 量測結果 . . . . . . . 81
4.4.3 layout option 為 8n 8×50 µm 模擬結果 . . . . . . . 86
4.4.4 layout option 為 8n 8×50 µm 量測結果 . . . . . . . 90
4.4.5 layout option 為 8n 8×50 µm lumped element 模擬
結果 . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.4.6 layout option 為 8n 8×50 µm lumped element 量測
結果 . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.5 結果與討論 . . . . . . . . . . . . . . . . . . . . . . . 102
第五章結論 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
參考文獻 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

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指導教授

傅家相

審核日期

2024-8-15

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