摘要(英) |
In the thesis, we first analyze the jitter of digital circuits. We divide the jitter source into four categories: vdd / gnd bounce jitter, substrate noise jitter, data dependent jitter, and clock jitter.
For the frequently used flip-flop and MUX, we propose an architecture that has the least jitter. Also, sizing and layout techniques are used to decrease the jitter. In general, the measurement results of output waveform jitter consists of several kinds of jitter. For the D-flip-flop we propose an architecture that could accumulate the output jitter, except for clock jitter so that the output waveform mainly consist of output jitter, except for clock jitter. Design results show that the low-jitter architecture can achieve only 1.17ps and 0.04ps (peak-peak) for D-flip-flop and MUX respectively, using TSMC 0.18um CMOS technology. |
參考文獻 |
[1] Ji-Ren Y., Karlsson I., and C. Svensson, "A true single-phase-clock dynamic CMOS circuit technique", IEEE J. Solid-State Circuits, Vol22, pp.899-901, Oct 1987.
[2] Fiber Channel.Methodologies for jitter Specification, T11.2/Project 1230/Rev 10, June. 1999.
[3] M. Shimanouchi, "An approach to consistent jitter modeling for various jitter aspects and measurement methods", Proceedings. International Test Conference, pp.848-857, Nov. 2001.
[4] J. Yuan and C. Svensson, "New single-clock CMOS latches and flipflops with improved speed and power savings", IEEE J. Solid-State Circuits, Vol32 , pp.62-69, Jan. 1997.
[5] C. Piguet, “Logic circuit for bistable d-dynamic flip-flop.”, United States Patent, NO.4,057,741, November 1997.
[6] Gorre Verlag Konstanz Hartung., “The Design of High.Speed Dynamic CMOS Circuits for VLSI ,” Robert Rogenmoser, 1996.
[7] J. Yuan and C. Svensson, "Pushing the limits of standard CMOS", IEEE Spectrum, Vol28, pp.52-53, Feb. 1991
[8] H. Oguey and E. Vittoz, “CODYMOS Frequency dviders achive low power consumption and high frequency.” Electronic Letter, pp.386-387, August 1973.
[9] R. Rogenmoser, Q. Huang, F. Piazza, "1.57 GHz asynchronous and 1.4 GHz dual-modulus 1.2 μm CMOS prescalers" , IEEE Proceedings Custom Integrated Circuits Conference, pp.387-390, May 1994.
[10] R. Rogenmoser, N. Felber, Q. Huang, and W. Fichtner, "1.16 GHz dual-modulus 1.2 μm CMOS prescaler", IEEE Proceedings Custom Integrated Circuits Conference, pp.27.6.1-27.6.4 , May 1993
[11] B.Razavi,"Design of Integrated Circuits for Optical Communications," Mcgraw-hill publishers, 2003. |