| 摘要(英) |
In recent years, communication networks can provide high bit-rate transport over a shared medium with a serial line or link, such as passive optical networks, cable television networks (fiber, coaxial or hybrid), digital television, and wireless networks. These shared-medium networks typically use time, frequency or code division multiplexing to transport data signals from a central terminal to several remote customer terminals and from the customer terminals to the central terminal. Among them, time division multiple access (TDMA) is characterized by non-continuous or burst mode data transmission.
Traditionally, clock and data recovery (CDR) methodologies are provided for communications systems receiving continuous data streams that have enriched spectra at the sampling frequency. CDR is a useful functionality in high-speed transceivers. The received data are asynchronous and noisy, thus requiring that a clock be extracted for allowing synchronous operations. The data also need to be retimed so that jitter accumulated during data transmission can be removed.
The over-sampling techniques and phase picking algorithm are applied in this work. In addition, we try to give more creativity in the changing the architectures. In other phase picking methods, multiple bits are sampled in parallel to form a sliding window and have an average effect on the phase detection. The size of such a window defines how much information is extracted from the input data. It is a fixed design parameter. The bigger window size is suitable for the high frequency noise environment; the smaller size window has a better acquisition speed.
In this thesis, two all digital approaches of timing recovery techniques have been proposed. After the system level simulations of the two proposed methods, we can specify the system parameters and map to the real blocks in the circuit level. Both of them have been realized with tsmc 0.18μm 1P6M CMOS technology. |
| 參考文獻 |
Bibliography
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