1.8V 10 Gbps CMOS 串列式發射器及
內建式自我測試電路

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：40

、訪客IP：18.117.216.229

姓名

黃冠勝(Guan-Sheng Huang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

1.8V 10 Gbps CMOS 串列式發射器及內建式自我測試電路
(A 1.8V 10Gbps CMOS Data Serializer andBuilt-in Self-test Circuit )

相關論文

★ 運算放大器之自動化設計流程及行為模型研究	★ 2.5Gbps光纖收發機設計
★ 高速序列傳輸之量測技術	★ 使用低增益寬頻率調整範圍壓控震盪器之1.25-GHz八相位鎖相迴路
★ 類神經網路應用於高階功率模型之研究	★ 使用SystemC語言建立IEEE 802.3 MAC 行為模組之研究
★ 以回填法建立鎖相迴路之行為模型的研究	★ 一個2V 5GHz CMOS非整數頻率合成器與和差調變器設計
★ 適用於GHz頻段頻率合成器之CMOS電路技術	★ 高速傳輸連結網路的分析和模擬
★ 一個以取樣方式提供可程式化邏輯陣列功能除錯所需之完全觀察度的方法	★ 2.5Gbps CMOS串列式傳輸收發器設計
★ 抑制同步切換雜訊之高速傳輸器	★ 一個3.3V、8位元、每秒150百萬次取樣CMOS 類比數位轉換器
★ 以行為模型建立鎖相迴路之非理想現象的研究	★ 遞迴式類神經網路應用於序向電路之高階功率模型的研究

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

隨著網際網路和串列傳輸介面的蓬勃發展，有線串列式傳輸系統如光通訊收發系統、PCI-Express、serial-ATA、…等。串列式傳輸可減少傳輸線的數目，而使得所需要的面積、成本變少，更可減少了EMI效應。故高速的串列傳輸介面已逐漸取代平常使用之纜線及匯流排線，且隨著多媒體資訊應用日益廣泛，不論是應用在網際網路上資料傳輸之光通訊收發系統、電腦內的高速PCI-Express資料匯流排或是應用在儲存元件內的serial-ATA資料傳輸介面，使用者對資料傳輸頻寬的須求也日益增加，故在研究高效能、高傳輸速率、高整合性、低功率消耗及低成本之串列傳輸介面方面刻不容緩。
本論文之設計主要針對光纖通訊系統中的SONET OC-192規格中的串列式發射器為設計藍圖，在此發射器裡包含一個時脈倍頻電路及一個可將十六筆622.08Mbps的平行式資料轉成一筆9.9533Gbps串列式資料的串列多工器。時脈倍頻電路其功能依據SONET OC-192所確立之標準，由一622.08MHz本地振盪源經頻率合成產生八個均勻相位的1.24416GHz之輸出參考時脈信號的鎖相迴路電路。資料串列多工器利用時脈倍頻電路所產生的多相位時脈的時間相互關係，採用兩級式串列架構將十六筆622.08Mbps的平行式資料轉成一筆9.9533Gbps串列式資料，以逹到低功率消耗及低成本的設計。此電路採用TSMC 0.18μm CMOS製程技術，操作電壓為1.8V之下，總功率消耗為435毫瓦。
在收發系統中，收發器電路的傳輸錯誤率通常為其收發器效能的指標，由於現今收發系統發展快速，傳輸速率日益增高，在高速測試儀器也就水漲船高，測試成本也就高不可攀，然而內建試收發系統測試電路只須在晶片中增加一點面積即可立即測試出此晶片的效能，也為此收發系統大大的降低其量測成本。其中利用一偽亂碼產生器產生測試用的測試亂碼，再利用接收端本地的另一組偽亂碼產生器配合許多判斷及控制電路產生發射端相同的測試亂碼以利做傳輸錯誤率的判斷，再利用計數器統計結果。此電路採用TSMC 0.18μm CMOS製程技術設計，操作電壓為1.8V之下，最高可量測40Gbps 16對1的串列/解串列收發機，其可量測錯誤率為10-5~10-14的解析度，最高速時平均功率消耗為36毫瓦。

摘要(英)

The rapidly-growing volumes of data in telecommunication network have rekindled interest in high speed optical and electronic device and system. The serial-link transceiver system such as optical transceiver system, PCI-Express, serial-ATA、etc.. Because serial-link transmission is less transmission line, the effect of EMI, chip cost and area will be reduced. The cable and Bus will be replace by high speed serial-link transceiver. Wherever high speed serial-link transceiver apply to optical transceiver system in internet, high speed PCI-Express data Bus in computer and serial-ATA in storage component, the bandwidth requirement is increase day by day. Therefore, it is important to research high performance, high speed, high integration, low power consumption, and low cost serial-link transceiver side.
The subject of this thesis is the design for optical communication system which conform SONET OC-192 specification. The transmitter comprises a clock multiply unit(CMU) and a data serializer which transfer 16 parallel 622.08Mbps data to a 9.9533Gbps serial data. The function of clock multiply unit (CMU) is designed for SONET OC-192. Its function is to synthesize a 8 phase 1.24416GHz output signal from a 622.08MHz reference source. The data serailizer is adopted two stage architecture to transfer 16 parallel 622.08Mbps data to a 9.9533Gbps serial data by multi-phase relation to achieve a low power consumption and low cost design. The circuit is designed by TSMC 0.18μm CMOS process. The supply voltage is 1.8V. Total power consumption is 435mW.
The bit error rate (BER) is an index of transceiver system in general. Because the data rate of the transceiver system is increased quickly, the high speed test equipment is very expensive. Built-in test only need to add a small area in chip to test the chip performance. Therefore, the cost of testing will cost down vastly. In this design, a pseudo random bit sequence (PRBS) generator generates a test code in to device under test (DUT). And then, tester receives data form DUT to generate corresponding PRBS code to test bit error rate by decision block and control unit. Finally, the counter counts the number of error. The circuit is designed by TSMC 0.18μm CMOS process. The supply voltage is 1.8V. The highest operation of the tester is suit for 16:1 40Gbps serial-link transceiver. The resolution of the test is 10-5~10-14. Total power consumption is 36mW in highest speed operation.

關鍵字(中)

★ 壓控振盪器
★ 鎖相迴路
★ 時脈倍頻電路
★ 串列器
★ 發送器
★ 偽亂碼產生器
★ 自我測試電路

關鍵字(英)

★ BIST
★ PRBS generator
★ transmitter
★ serializer
★ CMU
★ PLL
★ VCO

論文目次

摘要 i
目錄 vi
圖目錄 viii
表目錄 x
第一章簡介 1
1.1 研究動機 1
1.2 SONET 收發器系統簡介 2
1.3 發射器架構 5
1.4 論文組織 6
第二章時脈倍頻電路 7
2.1 簡介 7
2.2 時脈倍頻電路架構 8
2.3 時脈倍頻電路線性模型 10
2.4 電壓控制振盪器 13
2.5 振盪器頻段控制電路 18
2.6 除頻器與相位頻率偵測器 22
2.7 電荷幫浦電路 26
2.8 迴路濾波器設計 28
2.9 模擬與量測結果 29
第三章資料序列器 36
3.1 簡介 36
3.2 資料序列器架構簡介 37
3.3 資料序列器架構設計 43
3.4 電路設計 48
3.5 模擬結果 51
第四章收發器自我測試電路 53
4.1 簡介 53
4.2 偽亂碼產生器原理 56
4.3 可程式化平行式偽亂碼產生器 60
4.4 自我測試電路 68
4.5 模擬與量測結果 74
第五章結論 83
參考文獻 86

參考文獻

[1] V. Schwarz, B. Willen, H. Jackel, “56Gbit/s Analogue PLL for Clock Recovery,” IEE Electronics Letters, vol. 37, No. 22, pp. 1336-1338, Oct. 2001.
[2] Hendarman et al., " STS-768 multiplexer with full-rate output data retimer in InP HBT," IEEE Journal of Solid-State Circuits, vol. 38, pp.1497-1503, Sept. 2003.
[3] T. Otsuji et al., “20-40-Gbit/s-Cllass GaAs MESFET Digital Ics for Future Optical Fiber Communications Systems,” International Journal of High Speed Electronics and Systems, vol.9, No. 2, pp. 399-435, 1998.
[4] Z. Lao et al., “20-40 Gbit/s GaAs-HEMT Chip Set for Optical Data Receiver,” International Journal of High Speed Electronics and Systems, vol.9, No. 2, pp. 437-472, 1998.
[5] M. Meghelli, " 132-Gb/s 4:1 multiplexer in 0.13-μm SiGe-bipolar technology," IEEE Journal of Solid-State Circuits, vol. 39, pp.2403-2407, December 2004.
[6] Hong-Ih Cong et al., “A 10-Gb/s 16:1 Multuplexer and 10-GHz Clock Synthesizer in 0.25-μm SiGe BiCMOS,” IEEE Journal of Solid-State Circuits, vol.36, No. 12, pp. 1946-1953, Dec. 2000.
[7] M. Meghelli et al., “SiGe BiCMOS 3.3-V Clock and Data Recovery Circuits for 10-Gb/s Serial Transmission System,” IEEE Journal of Solid-State Circuits, vol.35, No. 12, pp. 1992-1995, Dec. 2000.
[8] Y. M. Greshishchev et al., “A Fully Integrated SiGe Receiver IC for 10-Gb/s Data Rate,” IEEE Journal of Solid-State Circuits, vol.35, No. 12, pp. 1949-1957, Dec. 2000.
[9] Y. M. Greshishchev et al., “SiGe Clock and Data Recovery IC with Linear-Type PLL for 10-Gb/s SONET Application,” IEEE Journal of Solid-State Circuits, vol.35, No. 9, pp. 1353-1359, September 2000.
[10] Satoshi Ueno et al., “A Single-Chip 10Gb/s Transceiver LSI using SiGe SOI/BiCMOS,” IEEE ISSCC, September 2001.
[11] G. Georgiou, Y. Baeyens et al., “Clock and Data Recovery IC for 40-Gb/s Fiber-Optical Receiver,” IEEE Journal of Solid-State Circuits, vol.37, No. 9, pp. 1120-1125, September 2002.
[12] M. Meghelli et al., “50-Gb/s SiGe BiCMOS 4:1 Multiplexer and 1:4 Demultiplexer for Serial Communication System,” IEEE Journal of Solid-State Circuits, vol.37, No. 12, pp. 1790-1794, Dec. 2002.
[13] Ting-Ping Liu, “1.5V 10-12.5GHz Integrated CMOS Oscillators,” VLSI Circuits Design of technical papers, vol.9, No. 2, pp. 55-56, 1999.
[14] A. Tanabe et al., “0.18-μm CMOS 10-Gb/s Multiplexer/Demultiplexer ICs Using Current Mode Logic with Tolerance to Threshold Voltage Function,” IEEE Journal of Solid-State Circuits, vol.36, No. 6, pp. 988-996, 2001.
[15] H. Knapp et al., “25 GHz Static Frequency Divider and 25Gb/s Multiplexer in 0.12μm CMOS,” IEEE Journal of Solid-State Circuits, pp. 302-303, February 2002.
[16] D. Kehrer et al., " 40-Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120-nm standard CMOS," IEEE Journal of Solid-State Circuits, vol. 38, pp.1830-1837, November 2003.
[17] M. Fukaishi, K. Nakamura et al., “A 20-Gb/s CMOS Multichannel Transmitter and Receiver Chip Set for Ultra-High-Resolution Digital Displays,” IEEE Journal of Solid-State Circuits, vol.35, No. 11, pp. 1611-1618, 2000.
[18] J. Savoj, B. Razavi, “A 10-Gb/s CMOS Clock and Data Recovery Circuit With a Half-Rate Binary Phase/Frequency Detector,” IEEE Journal of Solid-State Circuits, vol.38, No. 1, pp. 13-21, 2003.
[19] Jun Cao, M. Green et al., “OC-192 Transmitter and Receiver in Standard 0.18-μm CMOS,” 2002 IEEE International Solid-State Circuits, Volume 1 , 3-7 Feb. 2002.
[20] Jonathan E. Rogers, and John R. Long, “A 10Gb/s CDR/DEMUX with LC Delay Line VCO in 0.18μm CMOS,” IEEE ISSCC, pp. 254-255, 2002.
[21] C. –L. Kuo, “ A 1.8V 10GHz CMOS Frequency Synthesizer “ Master’s thesis, National Central University, Institute of Electronics Engineering, June 2002.
[22] B. Razavi, “A Study of Phase Noise in CMOS Oscillators,” IEEE Journal of Solid-State Circuits, VOL. 31, NO.3, pp. 331-343, March 1996.
[23] J. –H. You, “Clock Multiplier Unit and Clock/Data Recovery for OC-192 Transceiver “ Master’s thesis, National Central University, Institute of Electronics Engineering, June 2003.
[24] C. –C. Liu, “ A 1.8V CMOS OC-192 Transmitter “ Master’s thesis, National Central University, Institute of Electronics Engineering, June 2003.
[25] R. E. Best, “Phase-Locked Loops: Design, Simulation, and Applications,” New York: McGraw-Hill, Fourth Ed., 1999.
[26] S. –J. Lee et al., “A fully integrated Low-noise 1-GHz frequency synthesizer design for mobile communication application,” IEEE Journal of Solid-State Circuits, VOL. 32, NO.5, pp. 760-765, May 1997.
[27] C. -H. Park et al., “A Low-noise, 900MHz VCO in 0.6μm CMOS,” IEEE Journal of Solid-State Circuits, VOL. 34, NO.5, pp. 586-591, May 1999.
[28] S. –J. Lee et al., “A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme ,” IEEE Journal of Solid-State Circuits, VOL. 32, NO.2, pp. 289-291, Feb. 1997.
[29] Wei-Zen Chen, Chien-Liang Kuo, Chia-Chun Liu, “10 GHz quadrature-phase voltage controlled oscillator and prescaler ,” ESSCIRC 2003, 16-18 Sept. 2003.
[30] K. Sano et al., “50-Gbit/s 4-bit multiplexer/demultiplexer chip-set using InP HEMTs ,” Gallium Arsenide Integrated Circuit (GaAs IC) Symposium 2002. 24th Annual Technical Digest , 20-23 Oct. 2002.
[31] T. Nakura et al., “A 3.6-Gb/s 340-mW 16 :1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology ,” IEEE Journal of Solid-State Circuits, VOL. 32, NO.2, pp. 289-291, Feb. 1997.
[32] B. Razavi, “Design of integrated circuits for optical communications,” New York: McGraw-Hill, international Ed., 2003.
[33] Wei-Zen Chen, Meng-Chih Weng, “A 2.5Gbps serial-link data transceiver in a 0.35 μm digital CMOS technology ,” Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits 2004 , 4-5 Aug., 2004.
[34] R. Westcott, “testing digital data transmission system,” U. K. patent 1 281 390, 1972.
[35] CCITT Recommendation V.29 9600 bit per second modem standardized for use on point-to-point 4-wire leased telephone-type circuits.
[36] CCITT Recommendation O.150 Digital test patterns for performance measurements on digital transmissionequipment.
[37] CCITT Recommendation O.151 Error performance measuring equipment operating at the primary rate and above.
[38] CCITT Recommendation O.191 Equipment to measure the cell transfer performance of ATM connections.
[39] R. Malasani, C. Bourde , G. Gutierrez, “A SiGe 10-Gb/s multi-pattern bit error rate tester,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp.321-324 June 2003
[40] O. Kromat et al., “A 10Gb/s silicon bipolar IC for PRBS testing,” In Int. Solid-state Circuit conf. (ISSCC) 1996, Dig. Tech. papers,pp. 206-207.
[41] A. M. Shames, M. A. Bayoumi, “A novel high-performance CMOS 1-bit full-adder cell,” IEEE trans. on Circuit and System-II, vol. 47, No. 5, pp.478-481, 2000
[42] H. Takauchi et al., “A CMOS multichannel 10-Gbs transceiver,” IEEE Journal of Solid-State Circuits, vol.38, No. 12, pp. 2094-2100, 2003.
[43] H. S. Muthali et al., “A CMOS 10-Gbs SONET transceiver,” IEEE Journal of Solid-State Circuits, vol.39, No. 7, pp. 1026-1033, 2004.
[44] M. Meghelli et al., “A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems,” IEEE Journal of Solid-State Circuits, vol.38, No. 12, pp. 2147-2154, Dec. 2003.
[45] M. Bussmann et al., ” A 12.5 Gb/s Si bipolar IC for PRBS generation and bit error detection up to 25 Gb/s” 1993 IEEE ISSCC, pp.152 - 153, Feb. 1993.
[46] H. Wohlmuth et al., “A low power 13-Gb/s 2/sup 7/-1 pseudo random bit sequence generator IC in 120 nm bulk CMOS,”. SBCCI 2004. 17th Symposium on, 7-11 Sept. 2004 Page(s):233 - 236.
[47] A. Hajimiri, S. Limotyrakis, and T. H. Lee, “Jitter and phase noise in ring oscillators,” IEEE Journal of Solid-State Circuits, VOL. 34, NO.6, pp. 790-804, June 1999.
[48] Chengxin Liu, McNeill, J.A, “Jitter in oscillators with 1/f noise sources,” IEEE International Symposium on Circuits and Systems(ISCAS) 2004, VOL. 1, pp.I-773-6, May 2004.
[49] D. Kucharski, K. Kornegay, ” A 40Gb/s 2.5V 27-1 PRBS generator in SiGe using a low-voltage logic family ,” 2005 IEEE ISSCC, pp.340 – 341, Feb. 2005

指導教授

劉建男、陳巍仁
(Chien-Nan Liu、Wei-Zen Chen)

審核日期

2005-5-6

推文