內容定址記憶體之鄰近區域樣型敏感瑕疵測試演算法

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：90

、訪客IP：3.135.216.170

姓名

郭曜彰(Yao-Chang Kuo) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

內容定址記憶體之鄰近區域樣型敏感瑕疵測試演算法
(Test Algorithms for CAMs with Neighborhood Pattern-Sensitive Faults)

相關論文

★ 應用於三元內容定址記憶體之低功率設計與測試技術	★ 用於隨機存取記憶體的接線驗證演算法
★ 用於降低系統晶片內測試資料之基礎矽智產	★ 內嵌式記憶體中位址及資料匯流排之串音瑕疵測試
★ 用於系統晶片中單埠與多埠記憶體之自我修復技術	★ 用於修復嵌入式記憶體之基礎矽智產
★ 自我修復記憶體之備份分析評估與驗證平台	★ 使用雙倍疊乘累加命中線之低功率三元內容定址記憶體設計
★ 可自我測試且具成本效益之記憶體式快速傅利葉轉換處理器設計	★ 低功率與可自我修復之三元內容定址記憶體設計
★ 多核心系統晶片之診斷方法	★ 應用於網路晶片上隨機存取記憶體測試及修復之基礎矽智產
★ 應用於貪睡靜態記憶體之有效診斷與修復技術	★ 應用於內嵌式記憶體之高效率診斷性資料壓縮與可測性方案
★ 應用於隨機存取記憶體之有效良率及可靠度提升技術	★ 應用於特殊半導體記憶體之測試與可靠性設計技術

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

在這篇論文裡提出了兩個關於內容定址記憶體之鄰近區域樣型敏感瑕疵（NPSFs）測試演算法。第一個部分是針對二元內容定址記憶體（BCAMs）的測試演算法。與之前提出的演算法不同之處在於之前的演算法是針對第二型（Type-2）鄰近區域樣型敏感瑕疵，而提出的演算法是對於第一型（Type-1）鄰近區域樣型敏感瑕疵，並且不需要任何提高測試容易性的電路。所提出的演算法共需要177 1/3N+238 2/3B 讀取/寫入的動作去偵測靜態鄰近區域樣型敏感瑕疵（SNPSF），被動式鄰近區域樣型敏感瑕疵（PNPSFs），和主動式鄰近區域樣型敏感瑕疵（ANPSFs），對於一個NxB個位元的二元內容定址記憶體而言。
這篇論文的第二個部分是關於三元內容定址記憶體（TCAMs）之鄰近區域樣型敏感瑕疵測試演算法。在三元內容定址記憶體的測試鄰近區域樣型敏感瑕疵是比在二元內容定址記憶體困難，原因在於三元內容定址記憶體的特殊硬體結構。所提出的演算法利用有限制的兩類(two-group)方式，同樣可以偵測到第一型的靜態鄰近區域樣型敏感瑕疵（SNPSF），被動式鄰近區域樣型敏感瑕疵（PNPSFs），和主動式鄰近區域樣型敏感瑕疵（ANPSFs）。所提出的演算法需要288N讀取和寫入的動作去偵測所有定義的鄰近區域樣型敏感瑕疵。

摘要(英)

This thesis presents two algorithms for detecting neighborhood pattern-sensitive faults (NPSFs) for content addressable memories. The first part presents a test algorithm for binary content addressable memories (BCAMs) with NPSFs. Differ from previous works which test BCAMs with Type-2 NPSFs, the proposed test algorithms is for Type-1 NPSFs and the BCAM without inserting design-for-testability circuitry is assumed. The proposed test algorithm requires 177 1/3N+238 2/3B Read/Write/Compare operations to cover static, passive, and active NPSFs for an NxB-bit BCAM.
The second part of this thesis presents a test algorithm for ternary content addressable memories (TCAMs) with NPSFs. Testing NPSFs in TCAMs is more difficult than that in BCAMs due to the special TCAM cell structure. The proposed test algorithm can cover static, passive, and active Type-1 NPSFs by using constrained two-group methodology. The test algorithm requires 288N Read/Write operations to cover the defined NPSF.

關鍵字(中)

★ 內容定址記憶體
★ 測試演算法
★ 鄰近區域樣型敏感瑕疵

關鍵字(英)

★ Test Algorithm
★ Neighborhood Pattern-Sensitive Faults
★ CAM

論文目次

Chapter 1 Introduction 1
Chapter 2 Test Algorithm of NPSF for Binary CAMs 8
2.1 The Architecture of CAMs 8
2.2 Fault Models of NPSF for Binary CAMs 11
2.3 The Proposed NPSF Test Algorithm for Binary CAMs 14
2.4 Comparison Result 27
Chapter 3 Test Algorithms of NPSF for Ternary CAMs 29
3.1 Fault Models of NPSF for Ternary CAMs 29
3.2 The Proposed NPSF Test Algorithm for Ternary CAMs 32
3.3 Result 44
Chapter 4 Conclusions and Future Work 46
Appendix 47
Reference 88

參考文獻

[1] K.-L. Cheng, M.-F. Tsai, and C.-W. Wu, “Efficient neighborhood pattern-sensitive fault test algorithms for semiconductor memories”, in Proc. VLSI Test Symposium, April 2001, pp. 225-230.
[2] K.-L. Cheng, M.-F. Tsai, and C.-W. Wu, “Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 11, pp. 1328-1336, Nov. 2002.
[3] G.-M. Park, and H. Chang, “An extended march test algorithm for embedded memories”, in Proc. Sixth Asian Test Symposium (ATS), Nov. 1997, pp. 404 – 409.
[4] M. Franklin, and K.-K. Saluja, “Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 9, pp. 1081-1087, Sept. 1996.
[5] V. Yarmolik, Y. Klimets, and S. Demidenko, “March PS (23N) test for DRAM pattern-sensitive faults”, in Proc. Seventh Asian Test Symposium (ATS), Dec. 1998, pp. 354-357.
[6] D.-S. Suk, and S.-M. Reddy, “An algorithm to detect a class of pattern sensitive faults in semiconductor random access memories” in Proc. 9th Int. Fault-Tolerant Computing Symposium, 1979, pp. 219-225.
[7] A. J. van de Goor, “Testing semiconductor memories: theory and practice”, John Wiley & Sons, Chichester, England, 1991.
[8] D.-S. Suk, and S.-M. Reddy, “Test procedures for a class of pattern-sensitive faults in semiconductor random-access memories”, IEEE Trans. On Computers, vol. 29, no. 6, pp. 419-429, June 1980.
[9] J.-C. Lee, Y.-S. Kang, and S. Kang, “A parallel test algorithm for pattern sensitive faults in semiconductor random access memories”, in Proc. 1997 IEEE International Symposium on Circuits and Systems (ISCAS), June 1997, pp. 2721-2724.
[10] P. Mazumder, and J.-H. Patel, “Parallel testing for pattern-sensitive faults in semiconductor random-access memories”, IEEE Trans. on Computers, vol. 38, no. 3, pp. 394-407, March 1989.
[11] Y.-D. Hur, H.-M. Cho, J.-H. Lee, and S.-B. Cho, “Built-in self parallel testing for functional faults in megabit RAMs”, in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), June 1991, pp. 3090-3093.
[12] A.-J. van de Goor, and I.-B.-S.Tlili, ”Disturb neighborhood pattern sensitive fault”, in Proc. 15th IEEE VLSI Test Symposium, April 1997, pp. 37-45.
[13] D.-C. Kang, and S.-B. Cho, “An efficient built-in self-test algorithm for neighborhood pattern sensitive faults in high-density memories”, in Proc. the 4th Korea-Russia International Symposium on Science and Technology (KORUS), June 2000, pp. 218 – 223.
[14] R.-S. Sable, R.-P. Saraf, R.-A. Parekhji, and A.-N. Chandorkar, “Built-in self-test technique for selective detection of neighborhood pattern sensitive faults in memories”, in Proc. 17th International Conference on VLSI Design, 2004, pp. 753– 756.
[15] B.-F. Cockburn, “Deterministic tests for detecting scrambled pattern-sensitive faults in RAMs”, in Proc. IEEE International Workshop on Memory Technology, Design and Testing, Aug. 1995, pp. 117–122.
[16] P. Mazumder, and J.-H. Patel, “An efficient built-in self testing for random-access memory”, IEEE Trans. on Industrial Electronics, vol. 36, no. 2, pp. 246-253, May 1989.
[17] A.-A. Amin, A.-A. Hamzah, and R.-E. Abdel-Aal, “Generic DFT approach for pattern sensitive faults in word-oriented memories”, in Proc. IEEE Computers and Digital Techniques, May 1996, pp. 199-202.
[18] A. Chrisanthopoulos, G. Kamoulakos, Y. Tsiatouhas, and A. Arapoyanni, “A test pattern generation unit for memory NPSF built-in self test”, in Proc. the 7th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec. 2000, pp. 425-428.
[19] D. Ryan, and S. Xiaoling, “On testing of static neighborhood pattern sensitive faults”, in Proc. 1999 IEEE Canadian Conference on Electrical and Computer Engineering, May 1999, pp. 577-582.
[20] A. Chrisarithopoulos, T. Haniotakis, Y. Tsiatouhas, and A. Arapoyanni, “New test pattern generation units for NPSF oriented memory built-in self test”, in Proc. the 8th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Sept. 2001, pp. 749 – 752.
[21] Y.-S. Kang, J.-C. Lee, and S. Kang, “Built-in self test for content addressable memories”, in Proc. 1997 IEEE International Conference on Computer Design (ICCD), Oct. 1997, pp. 48-53.
[22] P. Mazumder, J.-H. Patel, and W.-K. Fuchs, “Methodologies for testing embedded content addressable memories”, IEEE Trans. on Computer-aided Design, vol. 7, no. 1, pp. 11-20, January 1988.
[23] I. Arsovski, T. Chandler, and A. Sheikholeslami, “A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme”, IEEE Journal of Solid-State Circuits, vol. 38, no. 1, pp.155-158, Jan. 2003.
[24] H. Miyatake, M. Tanaka, and Y. Mori, “A design for high-speed low-power CMOS fully parallel content-addressable memory macros”, IEEE Journal of Solid-State Circuits, vol. 36, no.6, pp. 956-968, June 2001.
[25] J.-F. Li, R.-S. Tzeng, and C.-W. Wu, “Testing and diagnosing embedded content addressable memories”, in Proc. IEEE VLSI Test Symposium (VTS), April 2002, pp. 389-394.
[26] J.-F. Li, and Y.-C. Kuo, “Testing ternary content addressable memories”, in Proc. 15th VLSI/CAD Symposium.
[27] K.-J. Lin, and C.-W. Wu, “Testing content-addressable memories using functional fault models and march-like algorithms”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 5, pp. 577-588, May 2000.
[28] J.-F. Li, and C.-K. Lin, “Modeling and testing comparison faults for ternary content addressable memories”, in Proc. IEEE VLSI Test Symposium (VTS), May 2005, pp. 60-65.
[29] T. Jamil, “RAM versus CAM”, in Proc. IEEE Potentials, May 1997, pp. 26-29.
[30] J. -F. Li, “Testing comparison faults of ternary cams based on comparison faults of binary cams”, in Proc. IEEE Asia South Pacific Design Automation Conference, (ASP-DAC), Jan. 2005, pp. 65-70.

指導教授

李進福(Jin-Fu Li)

審核日期

2006-1-18

推文