用於修復嵌入式記憶體之基礎矽智產

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姓名

黃昭達(Chao-Da Huang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

用於修復嵌入式記憶體之基礎矽智產
(An Infrastructure IP for Repairing Embedded Memories)

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摘要(中)

大部分的系統晶片設計 (SoC) 裡包含了許多記憶體核心 (core)。而這些記憶體核心通常佔據了晶片絕大部分的面積。所以記憶體的良率通常主宰著整顆晶片的良率。記憶體內建自我修復 (built-in self-repair) 技術漸漸的被普遍用在提升記憶體良率上。在此論文中，我們提出了一個對於修復多個記憶體有效的內建自我修復電路。此內建式自我修復電路可以支援兩種冗餘架構 (備份行與備份列;備份行與備份IO). 由實驗結果可以得知我們所提出的記憶體內建自我修復電路的對於一個包含兩個備份列與四個備份行的8Kx64位元記憶體硬體負擔大約是2.19%。而且我們所提出的演算法修復率很接近
我們也提出了一個用於嵌入式記憶體測試與修復的基礎矽智產 (infrastructure IP)。此基礎矽智產包含一個指令記憶體 (instruction memory)，一個內建自我修復微處理器 (BISR processor)，多個支援不同大小記憶體的封套 (wrapper) 電路。此基礎矽智產可以同時測試在系統晶片內多個不同大小的記憶體。它也可以執行記憶體診斷與多種冗餘分析演算法。使用我們所定義的指令集可以大幅的減少記憶體測試與修復的時間。與微處理器基礎（processor-based）的記憶體自我修復方法比較，我們所提出的基礎矽智產測試時間的確大幅減少。而且可以改變測試與修復演算法的彈性也比傳統的記憶體自我修復方法來的高許多。實驗結果顯示用微處理器基礎自我修復方法實行LRM（local repair-most）演算法需要2320Nf　週期，其中Nf代表錯誤字元(word)的數目。用所提出的基礎矽智產只需要(NSR+NSC+NSF)Nf週期，其中NSR (NSC)代表備份列(行)的數目、NSF是封套電路傳送資訊到內建自我修復微處理器的週期數 (約為 )。其中內建自我修復微處理器對於包含三個備份列與三個備份行的硬體負擔大約是6926個閘極。封套電路對於一個包含三個備份列與三個備份行的8Kx64位元記憶體的硬體負擔大約是2.84%。

摘要(英)

Most system-on-chip (SoC) designs have many memory cores. These memory cores usually occupy most of the chip area. Thus the yield of memory cores usually dominates the yield of SoCs. Built-in self-repair (BISR) technique is gaining popular for improving the yield of memory cores. In this thesis, we propose an efficient BISR scheme for repairing multiple memory instances in SoCs. The BISR scheme can support two types of redundancy organizations (i.e., spare rows/spare columns and spare rows/spare IOs). Experimental results show that the area overhead of the proposed BISR is about 2.19% for an 8K×64-bit memory with two spare rows and four spare columns. Also, the repair rate of the proposed RA algorithm is close to the repair rate of the exhaustive algorithm.
We also present an infrastructure intellectual-property (IIP) for testing and repairing embedded memories. The IIP is composed of an instruction memory, a BISR processor and various wrappers for different memory sizes. The IIP can test multiple memory instances with different sizes concurrently in an SoC. It also can execute diagnosis and various redundancy analysis algorithms. The execution time of memory test and repair can be reduced significantly by using the defined instruction set. Compared with the processor-based BISR scheme [20], the test time of the proposed IIP is greatly reduced. Also, the flexibility of proposed IIP is higher than traditional dedicated BISR schemes. Experimental results show that the test time of executing local repair-most (LRM) algorithm [16] is 2320Nf cycles, where Nf is the number of faulty words. In the proposed IIP, it only needs (NSR+NSC+NSF)Nf cycles, where NSR (NSC) is the number of spare rows (columns) and NSF is the number of cycles of shifting the repair information from the Wrapper to the BISR Processor which is equal to . The area of the BISR Processor of the proposed IIP is about 6926 gates for a memory with three spare rows and threes spare columns. The area overhead of the Wrapper of the proposed IIP is about 2.84% for an 8K×64-bit memory with the three spare rows and three spare columns.

關鍵字(中)

★ 記憶體測試
★ 記憶體修復
★ 基礎矽智產

關鍵字(英)

★ memory test
★ memory repair
★ infrastructure IP

論文目次

Chapter 1 Introduction 1
Chapter 2 A BISR Scheme for Multiple SRAMs 6
2.1 BISR Architecture 6
2.2 Redundancy Architecture 8
2.3 Proposed RA Algorithm 9
2.4 BIRA Architecture 12
2.5 Verification Strategy 17
2.6 Experimental Results 20
Chapter 3 An IIP for Repairing Embedded Memories 28
3.1 Overall IIP Architecture 28
3.2 Instruction Set 33
3.2.1 Overview of March Algorithm 33
3.2.2 Instructions for Test and RA Algorithms 34
3.3 BISR Processor 40
3.3.1 Controller (CTR) 42
3.3.2 Built-In Redundancy-Analysis (BIRA) 44
3.4 Wrapper 46
3.4.1 Controller (CTR) 48
3.4.2 Address Remapping (AR) Circuit 49
3.5 Experimental Results 50
Chapter 4 Conclusions and Future Works 62
4.1 Conclusions 62
4.2 Future Works 63
Reference 64

參考文獻

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指導教授

李進福(Jin-Fu Li)

審核日期

2005-11-11

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