用於類比/混和訊號積體電路可靠度增強的加壓測試

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：55

、訪客IP：3.22.248.247

姓名

劉孟堯(Meng-Yao Liu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

用於類比/混和訊號積體電路可靠度增強的加壓測試
(Extreme Voltage Stress Test of Analog/Mixed Signal ICs for Reliability Enhancement)

相關論文

★ 應用於電容陣列區塊之維持比值良率的通道繞線法	★ 高速無進位除法器設計
★ 以正交分頻多工系統之同步的高效能內插法技術	★ 增強CMOS鎖相迴路可靠度
★ 適用於地面式數位電視廣播系統之平行架構記憶體式快速傅立葉轉換處理器設計	★ 對於長解碼長度可降低其記憶體使用的低密度同位檢查碼解碼器設計
★ 單級降壓式功因修正轉換器之探索	★ 設計具誤差消除機制之串疊式三角積分調變器
★ 交換電容式類比電路良率提升之設計方法	★ 使用分級時序記憶實作視角無關手勢辨識問題
★ 部分平行低密度同為元檢查碼解碼器設計	★ 應用於無線通訊系統之同質性可組態記憶體式快速傅立葉處理器
★ 低記憶體需求及效能改善的低密度同位元檢查碼解碼器架構	★ 混合式加法器設計
★ 非線性鋰電池之充放電模型	★ 降壓型轉換器之控制在市電併聯型光伏系統

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

至系統瀏覽論文 ( 永不開放)

摘要(中)

極電壓加壓測試系統架構已經發展出來，用於降低由閘極氧化層缺陷引起所失去的產能。但是，這個為了閘極氧化層發展出來的測試架構是以1 /E模型為基礎，這樣的缺陷模型適合氧化層厚度超過5nm的製程。在實際設計與製程上，.18?m或者以下製程，氧化層厚度會低於5nm，因此1/E缺陷模型可能是不適用的。在這項研究過程中，我們將考慮E缺陷模型。在此，氧化層厚度介於2.7nm到18.1nm之間範圍均適用。因此，本徵氧化層崩潰的壽命和故障率可以在某一壓力條件下被預測。本論文也說明產生加壓向量並且對電路上可加壓度低落的部分予以提升。ㄧ個使用另加的硬體的可加壓度提升策略也被提出。
為了去證明發展的極電壓測試技術，我們對於CMOS SRAM和PLL電路進行加壓測試的過程與應用。它顯示兩個電路可以在一些電晶體存在閘極氧化層缺陷的情況下透過傳統的Iddq測試，造成可靠度低落。因此，半導體製造商使用其它的加壓測試，在昂貴的熱燒過程中試驗，提升閘極氧化層的可靠度。然而，若使用此論文發展的壓力測試向量，兩個電路可被完全加壓。因此，能使電路全部閘極氧化層在極電壓壓力下測試下達到完全可靠度而不需使用昂貴的熱燒試驗。

摘要(英)

The framework of extreme-voltage stress test system has been developed to reduce the lost yield caused by gate-oxide defects. However, the framework was developed for the gate-oxide defects that assume with 1/E model, where such a defect model is applicable for the oxide thickness above 5nm. For practical designs with the process of .18 um or below, the oxide thickness is less than 5nm, and thus the defect model with 1/E model may not be applicable accurately. In this study, the defect model with E model will be considered, where the oxide thickness is ranged between 2.7nm to 18.1nm. Therefore, the lifetime and failure rate of intrinsic oxide breakdown can be predicted for a given stress condition.
This thesis demonstrates the methodology that generates the stress vector and deals with stressability enhancement of portions of the circuit having poor stressability. A stressability enhancement strategy using additional hardware is also presented.
In order to demonstrate the developed stress test generation process, we demonstrates the applications of such process to both CMOS SRAM and PLL. It will show that both circuits may pass the conventional Iddq-tests in the presence of gate-oxide defects that occur at some transistors, causing a low reliability. Therefore, semiconductor manufacturers need to take alternative stress tests, expensive burn-in tests, to enhance gate-oxide reliability. However, with the developed stress test vectors, both circuits are fully stressed. As a result, the circuit can achieve a full gate-oxide reliability under the extreme-voltage stress tests without the need of the expensive burn-in tests.

關鍵字(中)

★ 可靠度
★ 類比
★ 測試
★ 加壓

關鍵字(英)

★ stress
★ reliability
★ analog
★ test

論文目次

Chapter1 INTRODUCTION.................................................1
1.1 Motivation..............................................3
1.2 Organization............................................4
Chapter2 BRACKGROUND..................................................6
2.1 Physical Failure Mechanisms.............................6
2.1.1 Failure Mechanisms......................................6
2.1.2 CMOS Gate-Oxide Reliability.............................7
2.2 Defect Models...........................................10
2.2.1 Hole-Induced (1/E) Breakdown Model......................10
2.2.2 Thermochemical (E) Breakdown Model......................11
2.3 Extreme-Voltage Stress Tests............................12
2.4 Burn-in Tests...........................................16
2.5 Extreme-Voltage Stress Tests with 1/E model.............17
2.5.1 Stress Time and Stress Voltage..........................17
2.5.2 Stress Test Vector Generation...........................19
Chapter3 Stress Test of Analog Circuits with E model..................22
3.1 Stress Vector Generation................................22
3.1.1 Stress Test Vector Generation...........................23
3.1.2 Stress Time Calculation.................................24
3.2 Stressability Design Methodology........................26
3.2.1 Stressability Enhancement...............................26
3.2.2 Stress Time Reduction...................................28
3.2.3 Pin Overhead Reduction..................................34
Chapter4 Stress Test of CMOS Circuits for Reliability Enhancement.....39
4.1 Stress test for CMOS SRAM...............................39
4.1.1 SRAM Architecture and Its Component.....................39
4.1.2 Conventional Extreme-Voltage Stress Tests...............40
4.1.3 Developed Extreme-Voltage Stress Tests..................45
4.2 Stress Test for CMOS PLL................................53
4.2.1 PLL Architecture and Its Components.....................54
4.2.2 Conventional Extreme-Voltage Stress Tests...............59
4.2.3 Developed Extreme-Voltage Stress Tests..................62
4.3 Conclusion..............................................63
Chapter5 Conclusions and Future Work..................................67
5.1 Major Contributions.....................................67
5.2 Future Research Work....................................68
參考文獻...............................................................70

參考文獻

REFERENCES
[1] D.E. Swanson, “Forty years and looking forward,” Semiconductor International, vol. 11, no. 1, January 1988.
[2] A. Christou, Integrating Reliability into Microelectronics Manufacturing, John Wiley & Sons, Chichester, 1994.
[3] Technology Roadmap for Integrated Circuits used in Critical Applications, [Online] Available http://www.sandia.gov/eqrc/critical/critical.html, Septem -ber 1998.
[4] E.R. Hnatek, Integrated Circuit Quality and Reliability, 2nd Edition, Marcel Dekker, Inc., New York, 1995.
[5] C.F. Hawkins and J.M. Soden, “Electrical Characteristics and Testing Considerations for Gate Oxide Shorts in CMOS ICs,” Proc. International Test Conference, Philadelphia, PA, pp. 544-555, 1985.
[6] C.F. Hawkins and J.M. Soden, “Reliability and Electrical Properties of Gate Oxide Shorts in CMOS ICs,” Proc. International Test Conference, Washington, DC, pp. 443-451, 1986.
[7] M.H. Woods, “MOS VLSI Reliability and Yield Trends,” Proceedings of IEEE, vol.74, no. 12, pp.1715-1729, December 1986.
[8] T. Kim and W. Kuo, “Modeling Manufacturing Yield and Reliability,” IEEE Trans. on Semiconductor Manufacturing, Vol. 12, No. 4, pp. 485-492, November 1999.
[9] M. Syrzycki, “Modelling of Spot Defects in MOS transistors,” Proc. International Test Conference, Washington, DC, pp.148-157, 1987.
[10] P. Simon, J.M. Luchies, and W. Maly, “Identification of Plasma-Induced Damage Conditions in VLSI Designs,” IEEE Trans. on Semiconductor Manufacturing, vol. 13, no. 2, pp.136-144, May 2000.
[11] T. Brozek, V.R. Rao, A. Sridharan, J.D. Werking, Y.D. Chan, and C.R. Viswanathan, “Charge Injection Using Gate-Induced-Drain-Leakage Current for Characterization of Plasma Edge Damage in CMOS Devices,” IEEE Trans. on Semiconductor Manufacturing, vol. 11, no. 2, pp.211-216, May 1998.
[12] J.C. Lee, I. Chen, and C. Hu, “Modelling and Characterization of Gate Oxide Reliability,” IEEE Trans. on Electron Devices, vol. 35, no. 12, pp. 2268-2278, December 1988.
[13] K.F. Schuegraf and C. Hu, “Effects of Temperature and Defects on Breakdown Lifetime of Thin SiO2 at Very-Low Voltages,” Proc. IEEE International Reliability Physics Symp., San Jose, CA, pp.126-135, 1994.
[14] W. Kuo, W-T.K. Chien, and T. Kim, Reliability, Yield, and Stress Burn-in, A Unified Approach for Microelectronics Systems Manufacturing and Software Development, Kluwer Academic Publishers, Boston, 1998.
[15] T. Barrette, M. Stover and E. Sugasawara, “Evaluation of Early Failure Screening Methods,” Dig. of Papers, 1996 International Workshop on IDDQ Testing, Washington, DC, pp.14-17, 1996.
[16] R. Kawahara, O. Nakayama, and T. Kurasawa, “The Effectiveness of IDDQ and High Voltage Stress for Burn-in Elimination,” Dig. of Papers, International Workshop on IDDQ Testing, Washington, DC, pp.9-13, 1996.
[17] A.W. Righter, C.F. Hawkins, J.M. Soden, P. Maxwell, “CMOS IC Reliability Indicators and Burn-in Economics,” Proc. International Test Conference, Washington, DC, pp.194-203, 1998.
[18] T.Y.J. Chang and E.J. McCluskey, "SHOrt Voltage Elevation (SHOVE) Test for Weak CMOS ICs," Proc. VLSI Test Symposiums, Monterey. pp. 446-451, 1997.
[19] T.Y.J. Chang and E.J. McCluskey, "SHOrt Voltage Elevation (SHOVE) Test," Dig. of Papers, IEEE International Workshop on IDDQ Testing, Washington, DC, pp. 45-49, 1996.
[20] M.A. Khalil and C.L. Wey, “High-Voltage Stress Test Paradigms of Analog CMOS ICs for Gate-Oxide Reliability Enhancement,” Proc. IEEE VLSI Test Symposium, pp. 333-338, 2001.
[21] C.L. Wey, “Design of Stressability of Analog ICs for Gate-Oxide Reliability Enhancement,” Proc. IEEE International Mixed-signal Testing Workshop, Spain, 2003.
[22] MOSIS parametric test results at http://www.mosis.org/cgi-bin /cgiwrap/umosis/ swp/params/hp-amos14tb/t07k-params.txt
[23] M.A. Khalil, Extreme-Voltage Stress Test of Analog CMOS ICs for Gate-Oxide Reliability Enhancement,” Ph.D. Dissertation, Department of Electrical and Computer Engineering, Michigan State University, 2002.
[24] C.L. Henderson, Time Dependent Dielectric Breakdown of Semiconductor Reliability, IEEE, UK, 2002.
[25] D. L. Crook, “Method of Determining Reliability Screens for Time Dependent Reliability Breakdown,” Proc. IEEE International Reliability Physics Sympo -sium, pp.1-4, 1979.
[26] M. Kimura, “Field and Temperature Acceleration Model for Time-Dependent Dielectric Breakdown,” IEEE Transactions on Electron Devices, Vol.46, No. 1, pp.220-229, Jan. 1999.
[27] T.Y.J. Chang and E.J. McCluskey, "SHOrt Voltage Elevation (SHOVE) Test for Weak CMOS ICs," Proc. VLSI Test Symposiums, pp. 446-451, 1997.
[28] R. Rajsuman, “Iddq testing for CMOS VLSI,” Proc. IEEE Volume 88, Issue 4, pp.544 – 568, 2000.
[29] M.A. Khalil and C.L. Wey, “Extreme-Voltage Stress Vector Generation of Analog CMOS ICs for Gate-Oxide Reliability Enhancement,” Proc. International Test Conference, Baltimore, MD, pp. 348-357, 2001.
[30] E.R. Hnatek, A Realistic View of VLSI Burn-in, IEEE, 1989.
[31] C. Hu and Q. Lu, “A Unified Gate Oxide Reliability Model,” Proc. IEEE Int’l Reliable Physics, pp.47-51, 1999.
[32] J.W. McPherson, J. Kim, A. Shanware, H. Mogul, and J. Rodriguez,“ Trends in the Ultimate Breakdown Strength of High Dielectric-Constant Materials,” IEEE Trans. on Electron Devices, Vol. 50, No.8, pp.1771-1778, August 2003.
[33] Mixed Signal Benchmark Operational Amplifier netlist, [Online] Available http://faculty.washington.edu/manisoma/madtest/benchmarks/OpAmp.htm, April 2001.
[34] C.G. Huang, "Design of Low-power CMOS Static RAMs". M.S. Thesis, Department of Electrical Engineering, National Taiwan University, 1998.
[35] K.H. Cheng, C.W. Lai, Y.L. Lo, “A CMOS VCO for 1V, 1GHz PLL Applica -tions,” Proc. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, pp.150-153, August 2004.
[36] C.H. Park and B. Kim, ”A Low-noise 900 MHz VCO in 0.6 μm CMOS” Proc. Symp. on VLSI Circuits, pp.28-29, June 1998.
[37] M. Renovell, J.M. Galliere, F. Azais and Y. Bertrand “Boolean and current detection of MOS transistor with gate oxide short,” Proc. International Test Conference, pp. 1039-1048, 2001.
[38] C.L. Wey and M.Y. Liu, “Stress Test Pattern Generation for Analog CMOS ICs,” Proceeding of VLSI/CAD Symposium, Ken-ding, Taiwan, Aug. 2004.
[39] C.L. Wey and M.Y. Liu; and S. Quan, “Stress Test of CMOS SRAMs for Reliability Enhancement,” Proc. IEEE International Mixed-Signal Test Workshop, Cannes, France, 2005.
[40] C.L. Wey, M.Y. Liu and S. Quan; “Reliability Enhancement of CMOS SRAMs,” Proc. IEEE Memory Technology, Design, and Testing Workshop, Taipei, 2005.
[41] C.L. Wey and M.Y. Liu, “Burn-In Stress Test of Analog CMOS ICs,” Proc. IEEE, Asian Test Symposium, Ken-ding, Taiwain, Nov. 2004.

指導教授

魏慶隆(Chin-Long Wey)

審核日期

2005-7-15

推文