應用於串列傳輸之2.5GB/s CMOS 超取樣資料回復電路

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：17

、訪客IP：3.21.97.61

姓名

卓峰信(Feng-Hsin Cho) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於串列傳輸之2.5GB/s CMOS 超取樣資料回復電路
(2.5GB/s CMOS Oversampling Data Recovery Circuit for Serial Link Application)

相關論文

★ 一種應用於觸控液晶顯示器的新型嵌入式開關	★ 多重相位之延遲鎖定迴路倍頻器設計與分析
★ 2.5Gbps串列收發器設計	★ 具低抖動與可適應式頻寬之自我偏壓鎖相迴路設計
★ 全數位任意責任週期之同步映射延遲電路	★ 全數位式互補金屬氧化半導自我取樣延遲線電路用於時脈抖動量測
★ 500MHz,30個相位輸出之鎖相迴路應用於三倍超取樣時脈回復系統	★ 設計於90奈米製程輸出頻率為100MHz-1GHz之具可適應性頻寬鎖相迴路
★ 高解析度可變動責任週期之同步複製延遲電路	★ 奈米CMOS晶片內序列傳輸之接收器
★ 奈米CMOS晶片內序列傳輸之送器	★ 基於鎖相迴路之多重相位脈波產生器
★ 低能量時脈儲存元件之分析、設計與量測	★ 具有預先增強器之Gbps串列連結傳送器及全數位超取樣資料回復器
★ 應用於10Gbps晶片系統傳輸鏈之低抖動自我校準鎖相迴路設計	★ 使用高精準度電流偵測技巧之高轉換效能同步互補式金氧半降壓切換式穩壓器

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

在網路以及電腦資料處理速度演進的帶動下，興起高速串列資料傳輸研究的潮流。鎖相迴路與時脈資料回復電路在運用常見有兩大類。其一是在乙太網路以及光纖網路上的應用(例如：10GBase-LX4、OC192等等)；另一方面則著重在有線或晶片內部的串列資料傳輸的應用(例如USB2.0、IEEE1394b、SERIAL-ATA、PCI-EXPRESS)，現有產品中PCI-Express V1目前之速率已高達2.5Gb/s，因此本論文以CMOS製程實現接收端之相關電路設計技術，目為實現一個在接收端2.5Gb/s資料回復電路。本論文提出一個使用3倍超取樣技術的資料回復電路，其功能是將串列的訊號轉換回平行的資料。藉由延遲鎖定迴路產生的相位，可對串列訊號做3倍取樣，此資料回復器不僅可決定出最佳的取樣點、亦可找到資料的起始位置。在決定最佳取樣點方面，應用數位電路控制來決策出最佳參考相位，進而得到資料的最佳取樣邊界(Margin)。本論文使用TSMC 0.18um 1P6M CMOS Process，設計出一個2.5Gbps傳輸率之資料回復電路。在2.5Gbps的資料率下可將串列資料成功的還原成四個625MB/s的並列輸出。此時核心電路的消耗功率為28.7mW

摘要(英)

Recently research on high speed link is more popular because of the progress of computer and network. The applications of phase locked loop and timing recovery are categorized to two types. One type is the application of Ethernet (such as 10GBase-LX4) and optical fiber (such as OC192 and OC768). Another is the application of Firewire (such as USB and IEEE1394) 、Chip to Chip and storage to storage (such as PCI-Express and Serial ATA).The available products of PCI-Express
X1 achieves the 2.5Gbps data transfer rate. Therefore, this thesis studies on the implementation and design of a 2.5GB/s data recovery circuit for high speed link in PCI-Express X1.
A 2.5GB/s data recovery circuit with 3 times oversampling technique is adopted.
Its main function is that to receive the serial input signal to parallel output. It samples data 3 times by the sampling clock generated from delay locked loop, so as to decide the best sampling point and data frames. It uses digital control circuit to realize the 3 times oversampling technique so that the input signal is sampled with the maximum timing margin.
A 2.5GBps data recovery system with 3 times oversampling technique has been designed and implemented by 0.18μm TSMC CMOS process. 2.5GBps data stream would be successfully received and synchronized to four parallel channels with 28.7mW power consumptions.

關鍵字(中)

★ 時脈資料回復
★ 資料回復

關鍵字(英)

★ data recovery
★ clock data recovery

論文目次

Table of Contents
Chapter 1 Introduction.......................................................1
1.1 Era of Data Transmission.................................................2
1.2 Thesis Organization......................................................3 Chapter 2 Fundamental of Data Transmission...................................4 2.1 Bus Links................................................................5 2.1.1 Limitation of Conventional Bus Links...................................5
2.1.2 Source Synchronous Interfaces..........................................7
2.1.3 High Speed Buses.......................................................8
2.2 Point-to-Point Links.....................................................9
2.3 Serial Links vs. Parallel Links.........................................12
2.4 Example of a Basic Link.................................................16 2.4.1 Transmitter...........................................................16 2.4.2 Channel...............................................................19 2.4.3 Receiver..............................................................22 Chapter 3 Data Recovery system Architecture.................................25 3.1 Timing Recovery Architectures...........................................26 3.1.1 PLL-based Timing Recovery Architecture................................29 3.1.2 Phase-picking-based Timing Recovery Architecture......................33 3.2 Bit-Error Rate..........................................................35 Chapter 4 The Building Blocks of the Tracking Data Recovery.................43 4.1 Data Recovery System Architecture.......................................44 4.2 Delay Locked Loop.......................................................48 4.2.1 Phase Frequency Detector..............................................48 4.2.2 Charge Pump and Loop Filter...........................................50 4.2.3 Voltage Control Delay Line............................................51 4.3 Preamp and Sampler......................................................53
4.4 Digital Control Circuit.................................................55 4.4.1 Decision Circuit......................................................55 4.4.2 Edge Detector.........................................................57 4.4.3 Phase Shifter.........................................................58 4.4.4 Phase Selector........................................................59 4.4.5 Divider and Synchronizer..............................................60 4.5 Simulation Result.......................................................62 Chapter 5 Chip Implementation...............................................67 5.1 Layout Consideration....................................................68 5.2 Problem of Simulation Result............................................69 5.3 The Modified Data Recovery Architecture.................................70 Chapter 6 Conclusion and Future work........................................72 6.1 Conclusion..............................................................73 6.2 Future Works............................................................74
REFERENCE 75

參考文獻

REFERENCE
[1] H.B. Bakoglu, “Circuits, Interconnections, and Packaging for VLSI,“ Addison- Wesley Publication Company, 1990.
[2] K. Donnelly, “A 660 MB/s interface megacell portable circuit in 0.3μm-0.7μm CMOS ASIC,” 1996 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp.290-291, Feb. 1996.
[3] M. Galles, et al., “Spider: a high-speed network interconnect, IEEE Micro, vol.17, no.1, pp. 34-39, Jan.-Feb. 1997.
[4] N. Kushiyama, et al., “A 500-megabyte/s data-rate 4.5M DRAM,” IEEE Journal of Solid-State Circuits, vol.28, no.4, pp. 490-498, Apr. 1993.
[5] E. Reese, et al., “A Phase-tolerant 3.8GB/s data-communication router for a multi-processor supercomputer backplane,” 1994 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp.296-297, Feb. 1994. [6] A. Mu, et al., “A 285 MHz 6-port Plesiochronous Router Chip with Non-Blocking Cross-Bar Switch” Proceedings of 1996 IEEE Symposium on VLSI Circuits, pp.136-137, Jun. 1996.
[7] J. Kusin, et al., “The Stanford FLASH Multiprocessor,＂ Proceedings of the 21st International Symposium on Computer Architecture, ISCA-94, pp. 274-284.
[8] N. McKeown, “Tina Tera: A Packer Switch Core,” IEEE Micro, vol.17, no.1, pp.26-33, Jan.-Feb. 1997.
[9] F. Tobagi, “Fast Packet Switch Architectures for Broad” Proceedings of the IEEE, vol.78, no.1, pp.133-167, Jan. 1990.
[10] K.H. Cheng, et al., "A Dual-slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop," IEEE Trans. on Circuits and Systems Part II, Analog and Digital Signal Processing. Vol.50, pp. 892-896. Nov. 2003.
Reference
[11] K.H. Cheng, et al., "A Low-power High-driving Ability Voltage Control Oscillator Used in PLL," International Journal of Electronics, vol. 91, no. 6, pp. 361-375, June 2004.
[12] K.H. Cheng, et al., "A Fast-Lock DLL with Power-On Reset Circuit," IEICE Trans. on Fundamentals, Vol.E87-A No.9, pp.2210-2220, Sep. 2004.
[13] R. Mooney, et al., “A 900Mb/s bidirectional signaling scheme,” IEEE Journal of Solid-State Circuits, vol.30, no.12, pp.1538-1543, Dec. 1995.
[14] T. Takahashi, et al., “A CMOS Gate Array with 600Mb/s Simutaneous Bidirectional I/O Circuits,” IEEE Journal of Solid-State Circuits, vol.30, no.12, pp.1544-1546, Dec 1995.
[15] C.K. Yang, et al., “A 0.8-μm CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links,” IEEE Journal of Solid-State Circuits, vol.31, no.12, pp.2015-2023, Dec. 1996.
[16] C.K. Yang, “Design of High-Speed Serial Links in CMOS,” Ph.D. Dissertation, Stanford University, 1998.
[17] K. Lee, et al., “A CMOS serial link for fully duplexed data communication,” IEEE Journal of Solid-State Circuits, Apr. 1995, vol.30, no.4, p. 353-64
[18] J. Christiansen, “An Integrated High Resolution CMOS Timing Generator Based on an Array of Delay Locked Loops,” IEEE Journal of Solid-State Circuits, Jul. 1996, vol.31, no.7, pp. 952-7
[19] N. Kushiyama, et al., “A 500-megabyte/s data-rate 4.5 M DRAM,” IEEE Journal of Solid-State Circuits, Apr. 1993. vol.28, no.4, p. 490-8
[20] P.J. Black, et al., “A 1-Gb/s, four-state, sliding block Viterbi decoder,” IEEE Journal of Solid-State Circuits, Jun. 1997, vol.32, no.6, p. 797-805
Reference
[21] M.J. Izzard, C.G. Thisell, “Low Power Analog Control Clock Synchronizer for 3Gb/s Data Retiming in ATM Applications,” TI ACS Report, Nov. 1994.
[22] H.O. Johansson, J. Yuan, C. Svensson, “A 4-GSamp/s Line-Receiver in 0.8µm CMOS,” 1996 Symposium on VLSI Circuits. Digest of Technical Papers, Jun. 1996, pp. 116-7
[23] Z. Lao, U. Langmann, “Design of a Low-Power 10Gb/s Si Bipolar 1:16 Demultiplexer IC,” IEEE Journal of Solid-State Circuits, Jan. 1996, vol.31, no.1, pp. 128-31
[24] S.J. Lee, B. Kim, K. Lee, “A Novel High Speed Ring Oscillator for Multi-Phase Clock Generation Using Negative Skewed Delay Scheme,” IEEE Journal of Solid- State Circuits, Feb. 1997, vol.32, no.2, pp. 289-91
[25] T.H. Lee, et al., “A 155MHz Clock Recovery Delay-and Phase-Locked Loop,” IEEE Journal of Solid-State Circuits, Dec. 1992, vol.27, no.12, p. 1736
[26] M. Kurisu, et al., “2.8-Gb/s 176-mW Byte-Interleaved and 3.0-Gb/s 118-mW Bit- Interleaved 8:1 Multiplexers with a 0.15-µm CMOS Technology,” IEEE Journal of Solid-State Circuits, Dec. 1996, vol.31, no.12, pp. 2024-9
[27] J. Proakis, et al., Communication Systems Engineering, Prentice Hall, New Jersey, 1994
[28] A. Leon-Garcia, Probability and Random Processes for Electrial Engineering, Addison-Wesley Publishing Co., New York, 1994
[29] PCI-SIG GROUP, "PCI-Express TM Base Specification Revision 1.0a"
[30] S. Kim, et al., “An 800 Mbps Multi-Channel CMOS Serial Link with 3x Oversampling” Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, pp.451-454, Feb. 1995.
Reference
[31] M. Soyuer, et al., “Frequency Limitation of a Conventional Phase-Frequency Detector”, IEEE Journal of Solid-State Circuits, vol. 25, pp.1019-1022, Aug. 1990.
[32] J. G. Maneatis, “Precise delay generation using coupled oscillators,” Ph. D. dissertation, Stanford University, June 1994.
[33] A. Boni, et al., “LVDS I/O interface for Gb/s-per-pin operation in 0.35-um CMOS”, IEEE Journal of Solid-State Circuits, vol.36, pp. 706-711, April 2001.
[34] A. Fiedler, et al., “A 1.0625Gbps transceiver with 2x-oversampling and transmit signal pre-emphasis”, in ISSCC Dig., pp. 238-239, February 1997. [35] M. G. Johnson, et al., ”A variable delay line PLL for CPU coprocessor synchronization,” IEEE Journal of Solid-State Circuits, Vol.23, No.5, pp. 1218-1223, Oct.1998
[36] K. Lee and Y. Shin, “1.04 gbd low EMI digital video interface system using small swing serial link technique”, IEEE Journal of Solid-State Circuits, vol.33, pp. 816-823, May 1998.

指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2005-7-21

推文