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姓名 江書育(Shu-Yu Jiang) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 在串列連接傳收器內的內建抖動測試電路設計與應用
(Built-in Jitter Measurement Circuits Designs and Applications in Serial-Link Transceivers)相關論文 檔案 [Endnote RIS 格式]
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摘要(中) 隨著時間解析度的增高，測試時間開始大量的增加，設計彈性也被大幅的限制。為了要突破這些侷限，內建抖動量測電路已開始被廣泛的使用於晶片上的訊號抖動分布量測。一般而言，時間量測技術可以被分成兩部分來探討，分別是開迴路與閉迴路的架構設計。
針對開迴路的架構，本文提出了一個25億赫茲的內建抖動量測系統，來量測串列連接傳收器內的時脈抖動。與單純的游標延遲線架構相比，本文所提出的游標卡尺與自動對焦方法，可以有限的減少48.78百分比的延遲單元面積，且具有寬廣的抖動量測範圍。而藉由使用傳統的步階掃瞄方法，計數器電路只使用了19乘以61平方微米的面積﹔藉由所提出的等效訊號取樣技術，則是移除了來自於取樣時脈的輸入訊號抖動轉換路徑。而本文除了在延遲單元與判斷電路裡，使用了可以剔除供應電壓變化的設計之外，也在整體晶片佈局、校準與測試時間上做了有效的改善，並藉由使用90奈米的互補式金氧半製程設計，使得整個核心電路只有0.5乘以0.15平方毫米的面積需求，並且也已使用5微微秒時間解析度與25億赫茲輸入時脈頻率的設計，來驗證整體系統在高斯與均勻抖動訊號分布上的準確度。此外,，電路的晶片製作也已經藉由90奈米與0.35微米的製程完成驗證。
而在閉迴路的架構裡，本文提出了一個可以同時解決面積消耗、製程偏移與供應電壓雜訊的內建抖動量測電路設計。這是因為在傳統的游標震盪器架構裡，雖然面積消耗的問題可以有效的被解決，但是常常也會因為製程與電壓偏移的出現，使得內建抖動量測電路裡，出現了更多的雜訊。因此，本文提出了一個具有路徑分離特性的游標捲曲迴路設計，這個閉迴路設計除了可以有效解決面積消耗的問題之外，也可以同時解決掉製程偏移與供應電壓雜訊所帶來的問題。此外，一個兼具有10位元計數器與位移暫存器功能的設計，也被用來解決晶片上腳位數目不足的問題。而本文所提的路徑分離游標單元，也被使用在傳統的反及閘連鎖電路裡，用來改善系統的準確度。此外，再藉由在傳導路徑上所增加的可控電容，改善了製程與供應電壓對於抖動量測電路所產生的影響。最後，為了消除電路裡無法避免的量測偏移，本文提出了一個校準流程，來控制閉迴路架構裡的製程與供應電壓補償電路。本閉迴路架構是採用0.18微米1層多晶矽與6層金屬的互補式金氧半製程設計，來驗證所提出的小巧且耐用的內建抖動量測電路設計，本設計除了具有500到1300兆赫茲的量測範圍之外，也只佔用了0.006平方毫米的晶片面積，且在5微微秒的時間解析度之下，除了可以達到至少95百分比的量測準確度之外，針對10億赫茲的輸入脈波訊號，功率消耗也只有1.7毫瓦。
摘要(英) The need for high timing resolution markedly increases test cost and limits feasible designs. To overcome these limitations, the built-in jitter measurement (BIJM) circuit is generally used to measure on-chip signal jitter distribution. Generally, the timing measurement techniques can be separated as two parts, open-loop and close-loop structures.
For the open-loop structure, a 2.5 GHz BIJM system is adopted to measure the clock jitter of the serial-link transceiver. The proposed Vernier caliper and autofocus approaches reduce the area cost of delay cells by 48.78 % relative to pure Vernier delay line (VDL) structure with a wide measurement range. The counter circuit occupies an area of 19 x 61 μm2 in the traditional stepping scan approach. The proposed equivalent-signal sampling technique removes the input jitter transfer path from the sampling clock. The supply voltage variation rejection design is incorporated into the delay cell and the judge circuit. The layout implementation, calibration, and test time of the proposed BIJM system are all improved. Core circuit occupies an area of only 0.5 x 0.15 mm2 with the 90 nm CMOS process. The Gaussian and uniform distributions jitters are verified at a 5 ps timing resolution and a 2.5 GHz input clock frequency. Further, chips implementation is also verified with the 90 nm and 0.35 μm CMOS process.
For the closed-loop structure, limitations of BIJM circuit designs include area cost, process variation and supply voltage noise. Conventional Vernier oscillator structure can solve the area cost problem. However, process and voltage variations always introduce noise into BIJM circuit. The proposed split path Vernier winding loop can solve the area cost, process variation and supply voltage noise at the same time. The 10-bit counter/shift register are applied to solve the pin count problem. The proposed split path Vernier cell is inserted into the conventional NAND gate chain for the accuracy improvement. By adding the controllable capacitors on the propagation paths, process and supply voltage variations only slightly affect jitter measurement result. Further, a calibration process is proposed to control the process and supply voltage compensation circuit and eliminate the un-avoidable measurement offset. All of these techniques were verified in the proposed compact and robust BIJM circuit by using the 0.18 μm 1P6M CMOS process. The 500–1300 MHz measurement range requires a chip area of only 0.006 mm2. Measurement accuracy exceeds 95 % for 5 ps timing resolution. Further, power consumption is just 1.7 mW for a 1 GHz input pulse signal.
關鍵字(中) ★ 抖動
★ 串列連接傳收器
★ 內建抖動測試關鍵字(英) ★ built-in jitter measurement
★ jitter
★ serial link transceiver論文目次 摘要--------------------------------------------------I
ABSTRACT----------------------------------------------III
CONTENTS----------------------------------------------V
LIST OF TABLES----------------------------------------VIII
LIST OF FIGURES---------------------------------------IX
CHAPTER 1 INTRODUCTION---------------------------------1
CHAPTER 2 FUNDAMENTALS OF JITTER MEASUREMENTS----------4
2.1. FUNDAMENTAL CIRCUITS-------------------------4
2.2. APPLICATION IN SERIAL LINK TRANSCEIVERS------9
CHAPTER 3 PROPOSED OPEN-LOOP BIJM CIRCUIT--------------12
3.1. PROPOSED OPEN-LOOP BIJM SYSTEM STRUCTURE-----12
3.2. DESIGN FOR AREA REDUCTION--------------------14
3.2.1. VERNIER CALIPER------------------------------14
3.2.2. AUTOFOCUS------------------------------------17
3.2.3. STEPPING SCAN--------------------------------19
3.3. DESIGN FOR ACCURACY IMPROVEMENT--------------22
3.3.1. EQUIVALENT-SIGNAL SAMPLING-------------------22
3.3.2. SUPPLY VOLTAGE VARIATION REJECTION-----------26
3.3.2.1 DELAY CELL-----------------------------------26
3.3.2.2 JUDGE CIRCUIT--------------------------------28
3.3.3. SMART LAYOUT STYLE---------------------------29
3.3.4. CALIBRATION AND TIME COST--------------------32
3.4. EXPERIMENTAL RESULTS-------------------------34
3.4.1. AREA REDUCTION-------------------------------34
3.4.2. ACCURACY IMPROVEMENT-------------------------37
3.5. CHIPS IMPLEMENTATION-------------------------41
3.5.1. 90 nm CMOS PROCESS---------------------------41
3.5.2. 0.35 μm CMOS PROCESS-------------------------45
3.5.3. DISCUSSION-----------------------------------47
CHAPTER 4 PROPOSED CLOSED-LOOP BIJM CIRCUIT------------48
4.1. PROPOSED CLOSED-LOOP BIJM SYSTEM STRUCTURE---48
4.2. DESIGN FOR AREA REDUCTION--------------------49
4.2.1. SPLIT PATH VERNIER WINDING LOOP--------------49
4.2.2. 10-STAGE COUNTER/SHIFT REGISTER--------------51
4.3. DESIGN FOR ACCURACY IMPROVEMENT--------------52
4.3.1. SPLIT PATH VERNIER CELL----------------------52
4.3.2. PROCESS AND SUPPLY VOLTAGE COMPENSATION------56
4.3.2.1. PROCESS COMPENSATION-------------------------57
4.3.2.2. SUPPLY VOLTAGE COMPENSATION------------------59
4.3.3. NAND GATE CHAIN------------------------------61
4.3.4. CALIBRATION----------------------------------62
4.4. EXPERIMENTAL RESULTS-------------------------64
4.4.1. AREA REDUCTION-------------------------------65
4.4.2. ACCURACY IMPROVEMENT-------------------------67
4.4.2.1. PROCESS VARIATION----------------------------67
4.4.2.2. SUPPLY VOLTAGE VARIATION---------------------68
4.4.2.3. NAND/MIXED-GATE CHAIN------------------------70
4.4.2.4. CALIBRATION----------------------------------72
4.4.3. SYSTEM VERIFICATION--------------------------73
CHAPTER 5 CONCLUSIONS AND FUTURE WORKS-----------------77
REFERENCES--------------------------------------------79
PUBLICATION LIST--------------------------------------82
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指導教授 鄭國興(Kuo-Hsing Cheng) 審核日期 2009-8-23 推文 plurk
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