一個新型全數位式高解析度可變責任週期之同步複製延遲電路

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許齊發(Chi-fa Hsu) 查詢紙本館藏

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電機工程學系在職專班

論文名稱

一個新型全數位式高解析度可變責任週期之同步複製延遲電路
(A New All-Digital High-Resolution Synchronous Mirror Delay with Arbitrary Duty Cycle)

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摘要(中)

當系統晶片所使用之頻率愈來愈高時，同步電路效能之好壞即會影響整體電路動作是否正常。因此，對於訊號同步電路亦愈重視。故有鎖相迴路（Phase-Locked Loop，PLL）及延遲迴路（Delay-Locked Loop，DLL）皆被廣泛運用於系統晶片內，但此兩種電路則需考慮幾項問題。第一為此兩種皆為閉迴路系統，故會有頻寬問題，需利用電容來增加電路之穩定性。第二點為此些電路需花幾百個時脈週期以上才能鎖定，於鎖定過程中需較大之功率消耗。
有鑒於此，因而發展出同步複製延遲電路（Synchronous Mirror Delay，SMD）以降低鎖定週期及功率消耗。但傳統式數位同步複製延遲電路有三項主要之缺點：其一為輸入訊號責任週期受到限制。其二為靜態相位誤差太大。其三就是電路會受到輸出負載改變之影響，使傳統式數位同步複製延遲電路只能運用於記憶體模組。
為使同步複製延遲電路能運用於更廣的範圍，因而提出一個新的數位同步複製延遲電路，本篇論文會針對上述之缺點做改善，並且輸入與輸出訊號間的靜態相位誤差≦16.6 ps，輸入訊號的責任週期可以任意調變(20%~80%)，並以TSMC 0.13μm製程實現晶片，可操作頻率為222~800MHz。當頻率為800MHz時的功率消耗為5.14mW、靜態相位誤差為8.07ps。核心電路的面積(不含I/O PAD)為0.015mm2。本篇論文後半段有佈局後之模擬結果，以證明的確可以改善上述之缺點。

摘要(英)

When the frequency of system clock is increasing in System-On-Chip (SoC), the efficiency of clock synchronization would affect the normal motion of the entire circuit. Therefore both Phase-locked Loop (PLL) and Delay-Locked Loop (DLL) are widely used in SoCs for many synchronization-dependent systems in order to suppress the clock skew. However, some issues shall be considered while using these two circuits. First of all, since it is closed-loop system, there would be problem of bandwidth, it rely on capacitance to increase the stability of the circuit. Secondly, these circuits would need hundreds clock cycles before locked, which consumed larger power during long locking process.
Consequently, synchronous mirror delay (SMD) is developed to reduce lock cycle and power consumption, and to replace PLL and DLL. However, there are three major defects in conventional SMD. Start with; the duty cycle for input signal is restricted. Next, the static phase error is large after locking. Finally, circuits would be affected by the change in output load, which makes the conventional synchronous mirror delay can be only used in memory module.
In order to enable synchronous mirror delay to be used in a wider range, a high precision fast locking arbitrary duty cycle clock synchronization circuit is introduced, which not only fix the defects of conventional SMD, but also gain the phase error between the input signal and output signal is less than 16.6 ps. And the tuning range of input signal’s duty cycle is 20% ~80%. The test chip is fabricated in a 0.13-μm, and the operating frequency is between 222~800MHz. It consumes 5.14mW and static phase error is 8.07ps when the frequency is 800MHz. The core area (without I/O PAD) is 0.015 mm2 , There will be a simulation result at the last half of this thesis, which confirms the proposed circuit has improved certainly these drawbacks of SMD.

關鍵字(中)

★ 同步電路
★ 同步複製延遲電路

關鍵字(英)

★ Synchronous Clock
★ Synchronous Mirror Delay
★ SMD

論文目次

摘要…………………………………………………………………………………… I
Abstract ……………………………………………………………………………. Ⅱ
致謝 ..………………………………………………………………………………. Ⅲ
目錄 ………………………………………………………………………………IV
圖目錄 …………………………………………………………………………...VI
表目錄 …………………………………………………………………………….VIII
第1章緒論 1
1.1 研究動機與目的 1
1.2 論文組織 5
第2章相關電路的分析 6
2.1 傳統式數位同步複製延遲電路架構 6
2.2 交錯式數位同步複製延遲電路架構 9
2.3 減少面積交錯式數位同步複製延遲電路架構 10
2.4 指揮偵測時脈偏斜式數位同步複製延遲電路 11
2.5 類比式之同步複製延遲電路 13
2.6 混合式同步複製延遲電路 14
2.7 連續近似暫存器數位同步延遲電路 16
2.8 總結 17
第3章新型高解析度同步複製延遲電路架構設計與動作原理 18
3.1 新型全數位式高解析度可變責任週期之同步複製延遲電路架構 18
3.2 新型全數位式高解析度可變責任週期之同步複製延遲電路原理 20
3.3 相位檢知器和環形移位器 22
3.3.1 相位檢知器電路分析與架構 22
3.3.2 環形移位器電路分析與架構 25
3.4 微調電路和多工選擇器 28
3.4.1 微調電路分析與架構 28
3.4.2 多工選擇電路分析與架構 30
3.5 新型全數位式高解析度可變責任週期之同步複製延遲電路與傳統式數位延遲複製電路架構之優缺點比較 31
第4章新型全數位式高解析度可變責任週期之同步複製延遲電路晶片模擬 33
4.1 新型高解析度可變責任週期之同步複製延遲電路模擬結果 33
4.1.1 新發表同步複製延遲電路操作頻率模擬結果 34
4.1.2 新發表同步複製延遲電路不同責任週期模擬結果 38
4.1.3 新發表同步複製延遲電路不同負載模擬結果 40
4.1.4 新發表同步複製延遲電路頻率改變模擬結果 42
4.1.5 新發表同步複製延遲加上IO Buffer模擬結果 44
4.2 晶片佈局圖及接腳定義圖 46
4.2.1 晶片佈局圖 46
4.2.2 晶片接腳定義圖 47
4.3 電路規格與比較表 50
4.4 量測考量 51
第5章結論與未來方向 53
5.1 結論 53
5.2 未來改進的方向 54
參考文獻……………………………………………………………………………55

參考文獻

[1] T. Saeki, Y. Nakaoka, M. Fujita, A. Tanaka, K. Nagata, K. Sakakibara, T. Matano, Y. Hoshino, K.Miyano, S. Isa, E. Kakehashi, J.M. Drynan, M. Komuro, T. Fukase, H. Iwasaki, J. Sekine, M. Igeta, N. Nakanishi, T. Itani, K. Yoshida, and H. Yoshino, S. Hashimoto, T. Yoshil, M. Ichinose, T. Imura, M. Uziie, K. Koyama, Y. Fukuzo, T. Okuda “A 2.5-ns Clock Access 250-MHz 256-Mb SDRAM with A Synchronous Mirror Delay,” IEEE ISSCC Dig. Tech. Paper, pp. 374-375, Feb. 1996.
[2] T. Saeki, H. Nakamura, and J. Shimizu “A 10ps Jitter 2 Clock Cycle Lock Time Cmos Digital Clock Generator Based on An Interleaved Synchronous Mirror Delay Scheme,” VLSI Circuits, Dig. Tech. Paper, pp. 109-110, Jun. 1997.
[3] Kihyuk Sung, Byung-Do Yang, and Lee-Sup Kim “Low Power Clock Generator Based on Area-reduced Interleaved Synchronous Mirror Delay,” Electronics Letters, vol. 38, no.9, pp. 399-400, Apr. 2002
[4] T. Saeki, K. Minami, H. Yoshida, and H. Suzuki “A Direct-skew-detect Synchronous Mirror Delay for Application-specific Integrated Circuits,” IEEE J. Solid-State Circuits, vol. 34, no 3, pp. 372-379, Mar. 1999.
[5] Daeyun Shim, Dong-Yun Lee, Sanghun Jung, Chang-Hyun Kim, and Wonchan Kim “An Analog Synchronous Mirror Delay for High-speed DRAM Application,” IEEE J. Solid-State Circuits, vol. 34, no 4, pp. 484-493, Apr. 1999.
[6] Chih-Hao Sun and Shen-Iuan Liu “A Mixed-Mode Synchronous Mirror Delay Insensitive To Supply And Load Variations,” Journal Of Analog Integrated Circuits And Signal Processings, vol. 39, pp. 75-80, Apr. 2004.
[7] Kihyuk Sung and Lee-Sup Kim “A High-resolution Synchronous Mirror Delay Using Successive Approximation Register,” IEEE J. Solid-State Circuits, vol. 39, no 11, pp. 1997-2004, Nov. 2004.
[8] Hung, Cheng-Liang; Wu, Chen-Lung and Cheng, Kuo-Hsing “Arbitrary Duty Cycle Synchronous Mirror Delay Circuits Design,” IEEE Asian Solid-State Circuit Conference, pp. 283-286, Nov. 2006.
[9] Daeyun Shim, Yeon-Jae Jung, Seung-Wook Lee, and Wonchan Kim “Fast Locking Clock Generator Using Analog Synchronous Mirror Delay Technique with Feedback Control,” Solid-State and Integrated-Circuits Technology, vol. 2, pp. 1125-1127, Oct. 2001.
[10] Seong-Jin Jang, Young-Hyun Jun, Jae-Goo Lee, and Bai-Sun Kon “ASMD With Duty Cycle Correction Scheme for High-Speed DRAM,” Electronics Letters, vol. 37, no.16, pp. 1004-1006, Aug. 2001.
[11] Jeong-Seok Chae, Daejeong Kim, and Dong Myeong Kim “Wide Range Single-Way-Pumping Synchronous Mirror Delay,” Electronics Letters, vol. 36, no.11, pp. 939-940, May 2000.
[12] Sei Hyung Jang “A New Synchronous Mirror Delay With An Auto-Skew-Generation circuit,” ISCAS, Vol. 5, pp. 397-400, May 2003.
[13] Tae-Sung Kim, Sung-Ho Wang, and Beomsup Kim “A Low Jitter, Fast Locking Delay Locked Loop Using Measure And Control Scheme,” Mixed-Signal Design, SSMSD, Southwest Symposium on, pp. 45-50, Feb. 2001.
[14] Yong Jin Yoon, Hyuck In Kwon, Jong Duk Lee, Byung Gook Park, Nam Seog Kim, Uk Rae Cho, and Hyun Guen Byun “Synchronous Mirror Delay For Multiphase Locking,”IEEE J. Solid-State Circuits, vol. 39, no 1, pp. 150-156, Jan. 2004.
[15] Yi-Ming Wang and Jinn-Shyan Wang “A Low-power Half-Delay-Line Fast Skew-Compensation Circuit,” IEEE J. Solid-State Circuits, vol. 39, no 6, pp. 906-918, Jun. 2004.
[16] Kuo-Hsing Cheng, Chen-Lung Wu, Yu-Lung Lo and Chia-Wei Su “A Phase-Detect Synchronous Mirror Delay For Skew-Compensation Circuit,” IEEE International Symposium on Circuits and Systems, vol.2, pp. 1070-1073, May 2005.
[17] Kuo-Hsing Cheng, Chen-Lung Wu, Chia-Wei Su and Yu-Lung Lo “A Phase-Locked Pulse Width Control Loop With Programmable Duty Cycle,” IEEE ASIA-PACIFIC Conference on ASIC, pp. 84-87, Aug. 2004.
[18] Hong, Kai-Wei, Lee Chien-Hsien, Cheng Kuo-Hsing, Wu Chen-Lung and Yang Wei-Bin “A Variable Duty Cycle with High-Resolution Synchronous Mirror Delay,” IEEE International Conference on Electronics, Circuits and Systems, pp. 569-572, Dec. 2006.
[19] Nakaya Hiroaki, Sasaki Yasuhiko, Kato Naoki, Arakawa Fumio and Shimizu Toru “An Alternative Cyclic Synchronous Mirror Delay for Versatility in Highly Integrated SoC,” IEEE Asian Solid-State Circuit Conference, pp. 279-282, NOV. 2006.
[20] Tsung-Chu Huang, Gau-Bin Chang and Ling Li “Congruence Synchronous Mirror Delay,” IEEE International Symposium on Circuits and Systems, pp.2184-2187, May 2007.
[21] Zeng Xianjun, Ji Rong, Huang Shizhen, Chen Liang, Luo Gang and Zhang Junfeng “A Novel Clock Duty-Cycle Corrector of DSP Systems,” Congress on Image and Signal Processing, vol.2, pp.561-564, May 2008.

指導教授

鄭國興(Kuo-hsing Cheng)

審核日期

2009-1-19

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