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姓名 張凱斐(Kai-Fei Chang) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 設計於90奈米製程輸出頻率為100MHz-1GHz之具可適應性頻寬鎖相迴路
(A 100MHz-1GHz Adaptive Bandwidth Phase-locked Loop Designed in 90nm Process)相關論文 檔案 [Endnote RIS 格式]
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摘要(中) 隨著超大型積體電路設計在速度的效能上快速的增加，而現在的單位面積中所包含的電晶體越來越多，所導致的延遲相對提升，在晶片設計中精確的時序時脈是必須的，尤其目前朝向單晶片系統設計(System-on-Chip Design)，在不同的子電路方塊當中常常會發生工作相位不同，因此，在主時脈進入子電路方塊之前是需要鎖相迴路(PLL)做相位校準的動作，使得所有晶片內各子電路的工作時脈同相位。
鎖相迴路在設計上最大的挑戰，除了低抖動(low jitter)、快速鎖定、低功率消耗等效能上的改善外，固定的電路參數限制使得一般的鎖相迴路僅能使用在特定規格上的系統，而降低其應用性。而頻寬(Wn)、相位邊限(Phase margin)等等的系統參數，決定了鎖相迴路整個系統的抖動和穩定度(Stability)。本論文針對鎖相迴路的頻寬與相位邊限參數推導，提出一個鎖相迴路可隨著各式的輸入參考頻率(Reference frequency)與倍頻係數(Multiplication Factor)的不同，依舊達到最小的時脈抖動與確保系統穩定。是利用Switch-capacitor equivalent resistor、programmable inverse-linear current mirror等外加電路，可自動改變鎖相迴路中充電泵的電流以及迴路濾波器裡面的電阻值，以達寬範圍操作的鎖相迴路。並且探討鎖相迴路在90奈米製程下，充電泵的漏電電流與大倍頻係數對時脈抖動的影響，利用具增益放大器的充電泵來改善此現象。
本篇論文以UMC 90nm 1P9M CMOS製程來實現，工作電壓為1V。量測結果: 鎖相迴路的輸入參考頻率為1M~50MHz，倍頻係數為2-1023，輸出的操作頻率為100MHz-1GHz皆可鎖定，最大時脈抖動(peak-to-peak jitter)小於輸出頻率的15.5%，而在操作頻率為1GHz、倍頻係數為20的狀態下，全部功率消耗22mW。摘要(英) When the efficiency of the speed with the very large-scale integrated (VSLI) circuit increases fast, there are more and more transistors in the unit area, because of these, the timing delay is promoted relatively. The accurate clock is necessary in chip design, especially the SOC (System-on-chip) design is developed, however, there is often phase error or clock skew which generate asynchronous phenomenon in different sub-circuit blocks. In this reason, the phase locked loop (PLL) is used to correct the clock phase when the major clock inputs the sub-circuit, and it can lead the operation clock of the sub-circuit into the same clock phase.
The challenge in designing the PLL, besides the improvement of the performance like low jitter, fast locking, and low power consumption, the restrictions of fixed loop parameters make the normal PLL just used in the specific standards, and that reduces the applications of the PLL. The loop parameters such as loop bandwidth and phase margin determine jitter performance and system stability. According to the restrictions of the PLL, this thesis employs formula derives to find the relationship between the loop parameters. Furthermore, we propose the architecture of PLL that can be adjusted to minimize jitter and to guarantee the stability with the reference frequency and multiplication factor. We use switch-capacitor equivalent resistor and programmable inverse-linear current mirror to adjust the current of charge pump and the resistor of loop filter in PLL for wide range operation. In the discussion of leakage current and large multiplication of PLL for 90nm process, we use the charge pump with OP amp to improve the effect.
We use the UMC 90nm 1P9M CMOS process with 1-voltage supply voltage in this thesis. The measurement results is that the oscillator output of this PLL is locked between 100MHz and 1GHz when the input reference frequency is 1MHz-50MHz and multiplication factor is 2-1023 and the peak-to-peak jitter is less than 15.5% of output frequency. The total power consumption of the proposed PLL is 22mW at 20 multiplication factor, 1GHz operation frequency.關鍵字(中) ★ 90奈米製程
★ 寬範圍操作
★ 鎖相迴路關鍵字(英) ★ 90nm process
★ PLL
★ wide range operation論文目次 Abstract ii
Table of Contents iv
List of Figures vii
List of table x
Chapter 1
1.1 Motivation 1
1.2 Function of the Adaptive Bandwidth PLL 2
1.3 Thesis Overview 2
Chapter 2
2.1 PLL Background Theory 4
2.1.1 Phase Frequency Detector (PFD) 5
2.1.2 Charge Pump (CP) 6
2.1.3 Loop Filter (LF) 8
2.1.4 Voltage-Controlled Oscillator (VCO) 8
2.1.5 Frequency Divider (FD) 9
2.2 High performance PLL examples 10
2.2.1 A Dual-Slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop 11
2.2.2 A Stabilization Technique for Phase-Locked Frequency Synthesizers 12
2.2.3 Self-Biased High-Bandwidth Low-jitter 1-to-4096 Multiplier Clock Generator PLL 14
Chapter 3
3.1 PLL Linear Model Analysis 16
3.2 The loop bandwidth and phase margin analysis of the PLL 17
3.3 The Mathematics Analysis of Adaptive Bandwidth PLL 23
3.3.1 The Symmetric Load 23
3.3.2 The Equivalent Resistor in LF 25
3.3.3 Multistage Inverse-Linear Current Mirror 27
3.3.4 Adaptive Bandwidth PLL 28
3.4 Behavior Model Simulation of the Adaptive Bandwidth PLL 31
Chapter 4
4.1 Architecture of the Proposed PLL 38
4.2 Phase Frequency Detector (PFD) 39
4.3 the Analysis of Leakage Current in Nano-scale Process 41
3.3.1 Charge Pump with OP amp circuit 44
4.4 Switch Capacitor Equivalent Resistor 45
4.5 Voltage Control Oscillator (VCO) 47
4.6 Multistage Inverse-linear Current Mirror 51
4.7 Programmable Divider 52
4.8 Post-simulation Results and Layout 53
4.8.1 The PLL simulation of Charge Pump with OP Amp or without OP Amp 54
4.8.2 Output Frequency: 100MHz; Multiplication Factor: N=2, 20 55
4.8.3 Output Frequency: 500MHz; Multiplication Factor: N=10 57
4.8.4 Output Frequency: 1GHz; Multiplication Factor: N=20, 1000 58
4.8.5 Layout and the Specification Table 60
Chapter 5
5.1 Measurement Results of PLL Locked State 65
5.1.1 Reference Frequency: 1MHz; Multiplication Factor: N=100, 1000 67
5.1.2 Reference Frequency: 15MHz; Multiplication Factor: N=7, 67 68
5.1.3 Reference Frequency: 40MHz; Multiplication Factor: N=3, 25 69
5.1.4 Reference Frequency: 50MHz; Multiplication Factor: N=2, 20 70
5.2 Measurement Results of PLL Jitter Histogram 72
5.2.1 The FOUT Jitter Histogram of PLL Using Conventional Charge Pump Compared with that of PLL Using Charge Pump with OP Amp 72
5.2.2 The Jitter Histogram of FOUT=1G, 900M, 600M, and 280MHz 73
5.3 Summary of Measurement Results 76
5.3.1 The Test Pattern for Input and Output Buffer 77
Chapter 6
6.1 Conclusions 79
6.2 Future Works 79
References 81參考文獻 [1] I. A. Young, J. K. Greason, and K. L. Wong, “A PLL clock generator with 5 to 110MHz of lock rang for microprocessors,” IEEE Journal of Solid-State Circuits, vol.27, pp.1599-1607, Nov. 1992.
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[20] Maneatis, J.G., Kim, J., McClatchie, I., Maxey, J., and Shankaradas, M., “Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL” IEEE Journal of Solid-State Circuits, vol.38, pp.1795-1803, Nov. 2003.
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[33] K. Minami, M. Fukaishi, M. Mizuno, H. Onishi, K. Noda, K. Imai, T. Horiuchi, H. Yamaguchi, T. Sato, K. Nakamura, M. Yamashina, “A 0.10um CMOS, 1.2V, 2GHz phase-locked loop with gain compensation VCO,” IEEE Int. Custom Circuits Conf., pp.213-216, May 2001.
[34] R. Holzer, “A 1V CMOS PLL designed in high-leakage CMOS process operating at 10-700MHz,” IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, vol.2, pp.220-482, Feb. 2002.指導教授 鄭國興(Kuo-Hsing Cheng) 審核日期 2006-7-17 推文 plurk
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